clk: exynos-audss: add support for Exynos 5420

The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>

diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 85b9e28078c84d0de19f861d33aff277671bebaf..180e8835569e9e017bb7148b83d3e5b79f5d0495 100644 (file)
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
 
 - compatible: should be one of the following:
   - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
-  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
-
+  - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+    SoCs.
+  - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+    SoCs.
 - reg: physical base address and length of the controller's register set.
 
 - #clock-cells: should be 1.
@@ -49,6 +51,7 @@ i2s_bus         6
 sclk_i2s        7
 pcm_bus         8
 sclk_pcm        9
+adma            10      Exynos5420
 
 Example 1: An example of a clock controller node using the default input
           clock names is listed below.

diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 19a0d874931e233264bc9998905c698f72b22711..884187fbfe00666ce109a5537e6c1b430f6359ae 100644 (file)
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,6 +19,12 @@
 
 #include <dt-bindings/clk/exynos-audss-clk.h>
 
+enum exynos_audss_clk_type {
+       TYPE_EXYNOS4210,
+       TYPE_EXYNOS5250,
+       TYPE_EXYNOS5420,
+};
+
 static DEFINE_SPINLOCK(lock);
 static struct clk **clk_table;
 static void __iomem *reg_base;
@@ -59,6 +65,16 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
 };
 #endif /* CONFIG_PM_SLEEP */
 
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+       { .compatible = "samsung,exynos4210-audss-clock",
+         .data = (void *)TYPE_EXYNOS4210, },
+       { .compatible = "samsung,exynos5250-audss-clock",
+         .data = (void *)TYPE_EXYNOS5250, },
+       { .compatible = "samsung,exynos5420-audss-clock",
+         .data = (void *)TYPE_EXYNOS5420, },
+       {},
+};
+
 /* register exynos_audss clocks */
 static int exynos_audss_clk_probe(struct platform_device *pdev)
 {
@@ -68,6 +84,13 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
        const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
        const char *sclk_pcm_p = "sclk_pcm0";
        struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
+       const struct of_device_id *match;
+       enum exynos_audss_clk_type variant;
+
+       match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
+       if (!match)
+               return -EINVAL;
+       variant = (enum exynos_audss_clk_type)match->data;
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        reg_base = devm_ioremap_resource(&pdev->dev, res);
@@ -83,7 +106,10 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
                return -ENOMEM;
 
        clk_data.clks = clk_table;
-       clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+       if (variant == TYPE_EXYNOS5420)
+               clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+       else
+               clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
 
        pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
        pll_in = devm_clk_get(&pdev->dev, "pll_in");
@@ -142,6 +168,12 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
                                sclk_pcm_p, CLK_SET_RATE_PARENT,
                                reg_base + ASS_CLK_GATE, 5, 0, &lock);
 
+       if (variant == TYPE_EXYNOS5420) {
+               clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+                               "dout_srp", CLK_SET_RATE_PARENT,
+                               reg_base + ASS_CLK_GATE, 9, 0, &lock);
+       }
+
        for (i = 0; i < clk_data.clk_num; i++) {
                if (IS_ERR(clk_table[i])) {
                        dev_err(&pdev->dev, "failed to register clock %d\n", i);
@@ -188,12 +220,6 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
        return 0;
 }
 
-static const struct of_device_id exynos_audss_clk_of_match[] = {
-       { .compatible = "samsung,exynos4210-audss-clock", },
-       { .compatible = "samsung,exynos5250-audss-clock", },
-       {},
-};
-
 static struct platform_driver exynos_audss_clk_driver = {
        .driver = {
                .name = "exynos-audss-clk",

diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f427c60f650d6f89486fdd2e72b3f3696178..0ae6f5a75d2a5abcffbfbef0ebbbc20e906f8ff2 100644 (file)
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
 #define EXYNOS_SCLK_I2S        7
 #define EXYNOS_PCM_BUS         8
 #define EXYNOS_SCLK_PCM        9
+#define EXYNOS_ADMA            10
 
-#define EXYNOS_AUDSS_MAX_CLKS  10
+#define EXYNOS_AUDSS_MAX_CLKS  11
 
 #endif