powerpc: Don't flush/invalidate the d/icache for an unknown relocation type

For an unknown relocation type since the value of r4 is just the 8bit
relocation type, the sum of r4 and r7 may yield an invalid memory
address. For example:
    In normal case:
             r4 = c00xxxxx
             r7 = 40000000
             r4 + r7 = 000xxxxx

    For an unknown relocation type:
             r4 = 000000xx
             r7 = 40000000
             r4 + r7 = 400000xx
   400000xx is an invalid memory address for a board which has just
   512M memory.

And for operations such as dcbst or icbi may cause bus error for an
invalid memory address on some platforms and then cause the board
reset. So we should skip the flush/invalidate the d/icache for
an unknown relocation type.

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Suzuki K. Poulose <suzuki@in.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/kernel/reloc_32.S b/arch/powerpc/kernel/reloc_32.S
index ef46ba6e094fa6f017d1e0ae38711e62dded190f..f366fedb08723036187657446bb1ac15d570d920 100644 (file)
--- a/arch/powerpc/kernel/reloc_32.S
+++ b/arch/powerpc/kernel/reloc_32.S
@@ -166,7 +166,7 @@ ha16:
        /* R_PPC_ADDR16_LO */
 lo16:
        cmpwi   r4, R_PPC_ADDR16_LO
-       bne     nxtrela
+       bne     unknown_type
        lwz     r4, 0(r9)       /* r_offset */
        lwz     r0, 8(r9)       /* r_addend */
        add     r0, r0, r3
@@ -191,6 +191,7 @@ nxtrela:
        dcbst   r4,r7
        sync                    /* Ensure the data is flushed before icbi */
        icbi    r4,r7
+unknown_type:
        cmpwi   r8, 0           /* relasz = 0 ? */
        ble     done
        add     r9, r9, r6      /* move to next entry in the .rela table */