drm/amdgpu: abstract TLB initialization for gfxhub/mmhub

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index e06f7a9e198536a25d1806ad584306b3df857b43..c55bf281f72f177111c453363adbfc77037eefeb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -114,6 +114,27 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
        WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
 }
 
+static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
+{
+       uint32_t tmp;
+
+       /* Setup TLB control */
+       tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
+
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+                           ENABLE_ADVANCED_DRIVER_MODEL, 1);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+                           SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+                           MTYPE, MTYPE_UC);/* XXX for emulation. */
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
+
+       WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+}
+
 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -131,35 +152,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
        /* GART Enable. */
        gfxhub_v1_0_init_gart_aperture_regs(adev);
        gfxhub_v1_0_init_system_aperture_regs(adev);
-
-       /* Setup TLB control */
-       tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL));
-       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
-       tmp = REG_SET_FIELD(tmp,
-                               MC_VM_MX_L1_TLB_CNTL,
-                               SYSTEM_ACCESS_MODE,
-                               3);
-       tmp = REG_SET_FIELD(tmp,
-                               MC_VM_MX_L1_TLB_CNTL,
-                               ENABLE_ADVANCED_DRIVER_MODEL,
-                               1);
-       tmp = REG_SET_FIELD(tmp,
-                               MC_VM_MX_L1_TLB_CNTL,
-                               SYSTEM_APERTURE_UNMAPPED_ACCESS,
-                               0);
-       tmp = REG_SET_FIELD(tmp,
-                               MC_VM_MX_L1_TLB_CNTL,
-                               ECO_BITS,
-                               0);
-       tmp = REG_SET_FIELD(tmp,
-                               MC_VM_MX_L1_TLB_CNTL,
-                               MTYPE,
-                               MTYPE_UC);/* XXX for emulation. */
-       tmp = REG_SET_FIELD(tmp,
-                               MC_VM_MX_L1_TLB_CNTL,
-                               ATC_EN,
-                               1);
-       WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+       gfxhub_v1_0_init_tlb_regs(adev);
 
        /* Setup L2 cache */
        tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL));

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 3d775107ddae9d3c6ffdee9b3ab2d3c88b0ec5a6..3e25563ab30d65dd14d55b0147ffe30b710e3188 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -125,6 +125,27 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
        WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp);
 }
 
+static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
+{
+       uint32_t tmp;
+
+       /* Setup TLB control */
+       tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));
+
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+                           ENABLE_ADVANCED_DRIVER_MODEL, 1);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+                           SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
+                           MTYPE, MTYPE_UC);/* XXX for emulation. */
+       tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
+
+       WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp);
+}
+
 int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
        u32 tmp;
@@ -143,6 +164,7 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
        /* GART Enable. */
        mmhub_v1_0_init_gart_aperture_regs(adev);
        mmhub_v1_0_init_system_aperture_regs(adev);
+       mmhub_v1_0_init_tlb_regs(adev);
 
        /* Setup TLB control */
        tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL));