clk: sunxi: Fix sun8i-a23-apb0-clk divider flags

The APB0 clock on A23 is a zero-based divider, not a power-of-two based
divider.

Note that this patch does not apply cleanly to kernels before 4.5-rc1,
which added CLK_OF_DECLARE support to this driver.

Fixes: 57a1fbf28424 ("clk: sunxi: Add A23 APB0 divider clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c
index 7ba61103a6f539d8f7e8ffd25c70f0d1025c3a6f..2ea61debffc180162d51cc437b173dc4ee831890 100644 (file)
--- a/drivers/clk/sunxi/clk-sun8i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -36,7 +36,7 @@ static struct clk *sun8i_a23_apb0_register(struct device_node *node,
 
        /* The A23 APB0 clock is a standard 2 bit wide divider clock */
        clk = clk_register_divider(NULL, clk_name, clk_parent, 0, reg,
-                                  0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
+                                  0, 2, 0, NULL);
        if (IS_ERR(clk))
                return clk;