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arm: omap: irq: define INTC_ILR0 register
authorFelipe Balbi <balbi@ti.com>
Tue, 9 Sep 2014 00:54:32 +0000 (17:54 -0700)
committerTony Lindgren <tony@atomide.com>
Thu, 11 Sep 2014 20:03:32 +0000 (13:03 -0700)
this is currently used as a hardcoded 0x100
offset.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/irq.c patch | blob | blame | history

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index ae082c60344552622e9ba02f5ebcc9370b056ff1..bae03290cad4ca3c545bc672e29ee07ddea0be2c 100644 (file)
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -41,6 +41,7 @@
 #define INTC_MIR_CLEAR0                0x0088
 #define INTC_MIR_SET0          0x008c
 #define INTC_PENDING_IRQ0      0x0098
+#define INTC_ILR0              0x0100
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG       32