ARM: dts: r8a7794: Remove unnecessary clock-output-names properties

* Fixed rate and fixed factor clocks do not require an
  clock-output-names property.
* Since 07705583e920fef6 ("clk: shmobile: div6: Make clock-output-names
  optional") Renesas div6 clocks do not require a clock-output-names
  property.

In the above cases there is only one clock output and its name is taken
from that of the clock node.  Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index eacb2b291361ec5cb7c5efbaa2812c316059fbee..7d7d18766540cceb267a5f2ff07a784a40ac3d88 100644 (file)
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -836,12 +836,11 @@
                ranges;
 
                /* External root clock */
-               extal_clk: extal_clk {
+               extal_clk: extal {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        /* This value must be overriden by the board. */
                        clock-frequency = <0>;
-                       clock-output-names = "extal";
                };
 
                /* External SCIF clock */
@@ -865,173 +864,152 @@
                        #power-domain-cells = <0>;
                };
                /* Variable factor clocks */
-               sd2_clk: sd2_clk@e6150078 {
+               sd2_clk: sd2@e6150078 {
                        compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0 0xe6150078 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                       clock-output-names = "sd2";
                };
-               sd3_clk: sd3_clk@e615026c {
+               sd3_clk: sd3@e615026c {
                        compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0 0xe615026c 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                       clock-output-names = "sd3";
                };
-               mmc0_clk: mmc0_clk@e6150240 {
+               mmc0_clk: mmc0@e6150240 {
                        compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
                        reg = <0 0xe6150240 0 4>;
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
-                       clock-output-names = "mmc0";
                };
 
                /* Fixed factor clocks */
-               pll1_div2_clk: pll1_div2_clk {
+               pll1_div2_clk: pll1_div2 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <2>;
                        clock-mult = <1>;
-                       clock-output-names = "pll1_div2";
                };
-               zg_clk: zg_clk {
+               zg_clk: zg {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <6>;
                        clock-mult = <1>;
-                       clock-output-names = "zg";
                };
-               zx_clk: zx_clk {
+               zx_clk: zx {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <3>;
                        clock-mult = <1>;
-                       clock-output-names = "zx";
                };
-               zs_clk: zs_clk {
+               zs_clk: zs {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <6>;
                        clock-mult = <1>;
-                       clock-output-names = "zs";
                };
-               hp_clk: hp_clk {
+               hp_clk: hp {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <12>;
                        clock-mult = <1>;
-                       clock-output-names = "hp";
                };
-               i_clk: i_clk {
+               i_clk: i {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <2>;
                        clock-mult = <1>;
-                       clock-output-names = "i";
                };
-               b_clk: b_clk {
+               b_clk: b {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <12>;
                        clock-mult = <1>;
-                       clock-output-names = "b";
                };
-               p_clk: p_clk {
+               p_clk: p {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <24>;
                        clock-mult = <1>;
-                       clock-output-names = "p";
                };
-               cl_clk: cl_clk {
+               cl_clk: cl {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <48>;
                        clock-mult = <1>;
-                       clock-output-names = "cl";
                };
-               m2_clk: m2_clk {
+               m2_clk: m2 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <8>;
                        clock-mult = <1>;
-                       clock-output-names = "m2";
                };
-               rclk_clk: rclk_clk {
+               rclk_clk: rclk {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <(48 * 1024)>;
                        clock-mult = <1>;
-                       clock-output-names = "rclk";
                };
-               oscclk_clk: oscclk_clk {
+               oscclk_clk: oscclk {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <(12 * 1024)>;
                        clock-mult = <1>;
-                       clock-output-names = "oscclk";
                };
-               zb3_clk: zb3_clk {
+               zb3_clk: zb3 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
                        #clock-cells = <0>;
                        clock-div = <4>;
                        clock-mult = <1>;
-                       clock-output-names = "zb3";
                };
-               zb3d2_clk: zb3d2_clk {
+               zb3d2_clk: zb3d2 {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
                        #clock-cells = <0>;
                        clock-div = <8>;
                        clock-mult = <1>;
-                       clock-output-names = "zb3d2";
                };
-               ddr_clk: ddr_clk {
+               ddr_clk: ddr {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
                        #clock-cells = <0>;
                        clock-div = <8>;
                        clock-mult = <1>;
-                       clock-output-names = "ddr";
                };
-               mp_clk: mp_clk {
+               mp_clk: mp {
                        compatible = "fixed-factor-clock";
                        clocks = <&pll1_div2_clk>;
                        #clock-cells = <0>;
                        clock-div = <15>;
                        clock-mult = <1>;
-                       clock-output-names = "mp";
                };
-               cp_clk: cp_clk {
+               cp_clk: cp {
                        compatible = "fixed-factor-clock";
                        clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
                        #clock-cells = <0>;
                        clock-div = <48>;
                        clock-mult = <1>;
-                       clock-output-names = "cp";
                };
 
-               acp_clk: acp_clk {
+               acp_clk: acp {
                        compatible = "fixed-factor-clock";
                        clocks = <&extal_clk>;
                        #clock-cells = <0>;
                        clock-div = <2>;
                        clock-mult = <1>;
-                       clock-output-names = "acp";
                };
 
                /* Gate clocks */