drm/radeon/cik: Add macrotile mode array query
authorMichel Dänzer <michel.daenzer@amd.com>
Mon, 18 Nov 2013 09:26:00 +0000 (18:26 +0900)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 18 Nov 2013 14:19:36 +0000 (09:19 -0500)
This is required to properly calculate the tiling parameters
in userspace.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_drv.c
drivers/gpu/drm/radeon/radeon_kms.c
include/uapi/drm/radeon_drm.h

index 08aa58ef8d0a8d8cf74f870d98c98bffdb39b8c6..b43a3a3c90671911a4eaa0a7c5a260c42118df41 100644 (file)
@@ -2427,6 +2427,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                gb_tile_moden = 0;
                                break;
                        }
+                       rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
                        WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                }
        } else if (num_pipe_configs == 4) {
@@ -2773,6 +2774,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                gb_tile_moden = 0;
                                break;
                        }
+                       rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
                        WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                }
        } else if (num_pipe_configs == 2) {
@@ -2990,6 +2992,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                gb_tile_moden = 0;
                                break;
                        }
+                       rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
                        WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                }
        } else
index 4970ac0ebc80ede4de5b64bf4acd434aded8cf61..ecf2a3960c0786ca02fc3aef84afab61e0e6303f 100644 (file)
@@ -1982,6 +1982,7 @@ struct cik_asic {
 
        unsigned tile_config;
        uint32_t tile_mode_array[32];
+       uint32_t macrotile_mode_array[16];
 };
 
 union radeon_asic_config {
index 1aee32213f66f5abd9ec64a7760168181b7bff79..9f5ff28864f6e3ccf4f4736cc55307735d87a70a 100644 (file)
  *   2.32.0 - new info request for rings working
  *   2.33.0 - Add SI tiling mode array query
  *   2.34.0 - Add CIK tiling mode array query
+ *   2.35.0 - Add CIK macrotile mode array query
  */
 #define KMS_DRIVER_MAJOR       2
-#define KMS_DRIVER_MINOR       34
+#define KMS_DRIVER_MINOR       35
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
index fa42c81da50097833aa94b6420e75022502b0671..55d0b474bd371ae83f1cea0ec08d30504b371816 100644 (file)
@@ -449,6 +449,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                        return -EINVAL;
                }
                break;
+       case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
+               if (rdev->family >= CHIP_BONAIRE) {
+                       value = rdev->config.cik.macrotile_mode_array;
+                       value_size = sizeof(uint32_t)*16;
+               } else {
+                       DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
+                       return -EINVAL;
+               }
+               break;
        case RADEON_INFO_SI_CP_DMA_COMPUTE:
                *value = 1;
                break;
index 46d41e8b0dccec30ec5b52f6dc772bf9e3088dc6..2f3f7ea8c77b8a653b0972302ead53319f13e5fc 100644 (file)
@@ -981,6 +981,8 @@ struct drm_radeon_cs {
 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
 /* query if CP DMA is supported on the compute ring */
 #define RADEON_INFO_SI_CP_DMA_COMPUTE  0x17
+/* CIK macrotile mode array */
+#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY   0x18
 
 
 struct drm_radeon_info {