m68knommu: add definitions for the third interrupt controller on devices that don...

Extending the interrupt controller code in  intc-simr.c to support the third
interrupt controller on the m5441x means we need to add defines (as 0) for the
third interrupt controller on devices that don't have a third interrupt
controller.

Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 5a8b5e4da12b0bbc2b84d93d43bddb4f4a28f642..b1bc76f1deccf8fa1c25947b8a7022097d155c0f 100644 (file)
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -42,6 +42,9 @@
 #define MCFINTC1_SIMR       (0)
 #define MCFINTC1_CIMR       (0)
 #define        MCFINTC1_ICR0       (0)
+#define MCFINTC2_SIMR       (0)
+#define MCFINTC2_CIMR       (0)
+#define MCFINTC2_ICR0       (0)
 
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 29b66e21413a7170177e74129165325e6090e96f..8d860200a2f539dc74ee5dec94e8753f202b0d4b 100644 (file)
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -82,6 +82,9 @@
 #define        MCFINTC1_SIMR           0xFC04C01C
 #define        MCFINTC1_CIMR           0xFC04C01D
 #define        MCFINTC1_ICR0           0xFC04C040
+#define MCFINTC2_SIMR          (0)
+#define MCFINTC2_CIMR          (0)
+#define MCFINTC2_ICR0          (0)
 
 #define MCFSIM_ICR_TIMER1      (0xFC048040+32)
 #define MCFSIM_ICR_TIMER2      (0xFC048040+33)