[9610] fbdev: dpu20: implement DPU SFR dump function in CAL

Change-Id: I526f0ecd042a97d5f3ad6a841ef4ae6b09c65050
Signed-off-by: ChiHun Won <chihun.won@samsung.com>

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
index 53a91865782537f0b40933f0d12791c5a9935ea9..f5d5f4b51165bad76a379e58359d2e842f1c4cb4 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_cal.h
@@ -290,6 +290,9 @@ void decon_reg_release_resource(u32 id, struct decon_mode_info *psr);
 void decon_reg_config_wb_size(u32 id, struct decon_lcd *lcd_info,
                struct decon_param *param);
 
+/* DECON SFR dump */
+void __decon_dump(u32 id, void __iomem *regs, void __iomem *base_regs, bool dsc_en);
+
 /* DECON interrupt control */
 void decon_reg_set_int(u32 id, struct decon_mode_info *psr, u32 en);
 int decon_reg_get_interrupt_and_clear(u32 id, u32 *ext_irq);

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
index f6b251803ea4ea35e968652324191d984e0ba403..3d1061f0cadb8687e59d1ad2ecbb235ce5f2f6c7 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/decon_reg.c
@@ -2219,3 +2219,41 @@ int decon_check_supported_formats(enum decon_pixel_format format)
        return -EINVAL;
 }
 
+/* base_regs means DECON0's SFR base address */
+void __decon_dump(u32 id, void __iomem *regs, void __iomem *base_regs, bool dsc_en)
+{
+       decon_info("\n=== DECON%d SFR DUMP ===\n", id);
+       print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs, 0x620, false);
+
+       decon_info("\n=== DECON%d SHADOW SFR DUMP ===\n", id);
+       print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs + SHADOW_OFFSET, 0x304, false);
+
+       decon_info("\n=== DECON0 WINDOW SFR DUMP ===\n");
+       print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       base_regs + 0x1000, 0x340, false);
+
+       decon_info("\n=== DECON0 WINDOW SHADOW SFR DUMP ===\n");
+       print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       base_regs + SHADOW_OFFSET + 0x1000, 0x220, false);
+
+       if (dsc_en) {
+               decon_info("\n=== DECON0 DSC0 SFR DUMP ===\n");
+               print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                               base_regs + 0x4000, 0x80, false);
+
+               decon_info("\n=== DECON0 DSC1 SFR DUMP ===\n");
+               print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                               base_regs + 0x5000, 0x80, false);
+
+               decon_info("\n=== DECON0 DSC0 SHADOW SFR DUMP ===\n");
+               print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                               base_regs + SHADOW_OFFSET + 0x4000, 0x80, false);
+
+               decon_info("\n=== DECON0 DSC1 SHADOW SFR DUMP ===\n");
+               print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                               base_regs + SHADOW_OFFSET + 0x5000, 0x80, false);
+       }
+}
+

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h
index a389fad56596357b1890b807c3fd1b4f3efddd14..b864c41068465fb434b3a5f1e4a7e838e3571058 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_cal.h
@@ -138,10 +138,9 @@ void dpp_reg_configure_params(u32 id, struct dpp_params_info *p,
 void dpp_constraints_params(struct dpp_size_constraints *vc,
                                        struct dpp_img_format *vi);
 
-/* DPU DMA DEBUG */
-void dma_reg_dump_com_debug_regs(int id);
-void dma_reg_dump_debug_regs(int id);
-void dpp_reg_dump_debug_regs(int id);
+/* DPU_DMA, DPP DEBUG */
+void __dpp_dump(u32 id, void __iomem *regs, void __iomem *dma_regs,
+               unsigned long attr);
 
 /* DPU_DMA and DPP interrupt handler */
 u32 dpp_reg_get_irq_and_clear(u32 id);

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c
index 210de75fa88c6ea05bc85c5437884ea033c4bb47..49021a311db8ae0e4d341631beecb589805974cd 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dpp_reg.c
@@ -1130,7 +1130,7 @@ static void dpp_reg_dump_ch_data(int id, enum dpp_reg_area reg_area,
 }
 
 static bool checked;
-void dma_reg_dump_com_debug_regs(int id)
+static void dma_reg_dump_com_debug_regs(int id)
 {
        u32 sel[12] = {0x0000, 0x0100, 0x0200, 0x0204, 0x0205, 0x0300, 0x4000,
                0x4001, 0x4005, 0x8000, 0x8001, 0x8005};
@@ -1146,7 +1146,7 @@ void dma_reg_dump_com_debug_regs(int id)
        checked = true;
 }
 
-void dma_reg_dump_debug_regs(int id)
+static void dma_reg_dump_debug_regs(int id)
 {
        u32 sel_g[11] = {
                0x0000, 0x0001, 0x0002, 0x0004, 0x000A, 0x000B, 0x0400, 0x0401,
@@ -1190,7 +1190,7 @@ void dma_reg_dump_debug_regs(int id)
        }
 }
 
-void dpp_reg_dump_debug_regs(int id)
+static void dpp_reg_dump_debug_regs(int id)
 {
        u32 sel_g[3] = {0x0000, 0x0100, 0x0101};
        u32 sel_vg[19] = {0x0000, 0x0100, 0x0101, 0x0200, 0x0201, 0x0202,
@@ -1222,3 +1222,56 @@ void dpp_reg_dump_debug_regs(int id)
        dpp_info("-< DPP%d DEBUG SFR >-\n", id);
        dpp_reg_dump_ch_data(id, REG_AREA_DPP, sel, cnt);
 }
+
+static void dma_dump_regs(u32 id, void __iomem *dma_regs)
+{
+       dpp_info("\n=== DPU_DMA%d SFR DUMP ===\n", id);
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       dma_regs, 0x6C, false);
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       dma_regs + 0x100, 0x8, false);
+
+       dpp_info("=== DPU_DMA%d SHADOW SFR DUMP ===\n", id);
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       dma_regs + 0x800, 0x74, false);
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       dma_regs + 0x900, 0x8, false);
+}
+
+static void dpp_dump_regs(u32 id, void __iomem *regs, unsigned long attr)
+{
+       dpp_info("=== DPP%d SFR DUMP ===\n", id);
+
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs, 0x4C, false);
+       if (test_bit(DPP_ATTR_AFBC, &attr)) {
+               print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                               regs + 0x5B0, 0x10, false);
+       }
+       if (test_bit(DPP_ATTR_ROT, &attr)) {
+               print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs + 0x600, 0x1E0, false);
+       }
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs + 0xA54, 0x4, false);
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs + 0xB00, 0x4C, false);
+       if (test_bit(DPP_ATTR_AFBC, &attr)) {
+               print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                               regs + 0xBB0, 0x10, false);
+       }
+       print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs + 0xD00, 0xC, false);
+}
+
+void __dpp_dump(u32 id, void __iomem *regs, void __iomem *dma_regs,
+               unsigned long attr)
+{
+       dma_reg_dump_com_debug_regs(id);
+
+       dma_dump_regs(id, dma_regs);
+       dma_reg_dump_debug_regs(id);
+
+       dpp_dump_regs(id, regs, attr);
+       dpp_reg_dump_debug_regs(id);
+}

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_cal.h b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_cal.h
index 804b9e63d90c6ebc6f764d2be01416069398761d..09c231ad3664d792b2bde425df75d2eca66639bf 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_cal.h
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_cal.h
@@ -28,6 +28,13 @@ enum dsim_ppi {
        DSIM_2BYTEPPI,
 };
 
+struct dsim_regs {
+       void __iomem *regs;
+       void __iomem *ss_regs;
+       void __iomem *phy_regs;
+       void __iomem *phy_regs_ex;
+};
+
 /*************** DSIM CAL APIs exposed to DSIM driver ***************/
 /* DPHY system register control */
 void dpu_sysreg_select_dphy_rst_control(void __iomem *sysreg, u32 dsim_id, u32 sel);
@@ -67,4 +74,8 @@ void dsim_reg_set_mres(u32 id, struct decon_lcd *lcd_info);
 void dsim_reg_set_bist(u32 id, u32 en);
 
 void dsim_reg_set_cmd_transfer_mode(u32 id, u32 lp);
+
+/* DSIM SFR dump */
+void __dsim_dump(u32 id, struct dsim_regs *regs);
+
 #endif /* __SAMSUNG_DSIM_CAL_H__ */

diff --git a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
index d61ecc13e01556e33822e2100756e1ece9aa0dec..8a0a8543b7bf248eac2adf2b55af0d254424869e 100644 (file)
--- a/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
+++ b/drivers/video/fbdev/exynos/dpu20/cal_9610/dsim_reg.c
@@ -2029,3 +2029,14 @@ void dsim_reg_set_cmd_transfer_mode(u32 id, u32 lp)
 
        dsim_write_mask(id, DSIM_ESCMODE, val, DSIM_ESCMODE_CMD_LPDT);
 }
+
+void __dsim_dump(u32 id, struct dsim_regs *regs)
+{
+       /* change to updated register read mode (meaning: SHADOW in DECON) */
+       dsim_info("=== DSIM %d LINK SFR DUMP ===\n", id);
+       dsim_reg_enable_shadow_read(id, 0);
+       print_hex_dump(KERN_ERR, "", DUMP_PREFIX_ADDRESS, 32, 4,
+                       regs->regs, 0xFC, false);
+
+       dsim_reg_enable_shadow_read(id, 1);
+}