sh: Add support for SH7721 CPU subtype.
authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Wed, 26 Dec 2007 02:45:06 +0000 (11:45 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Mon, 28 Jan 2008 04:19:02 +0000 (13:19 +0900)
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
19 files changed:
arch/sh/Kconfig
arch/sh/Kconfig.debug
arch/sh/drivers/dma/Kconfig
arch/sh/drivers/dma/dma-sh.c
arch/sh/kernel/cpu/sh3/Makefile
arch/sh/kernel/cpu/sh3/probe.c
arch/sh/kernel/cpu/sh3/setup-sh7720.c
arch/sh/kernel/early_printk.c
arch/sh/kernel/setup.c
arch/sh/kernel/timers/timer-tmu.c
drivers/serial/sh-sci.c
drivers/serial/sh-sci.h
include/asm-sh/cpu-sh3/cache.h
include/asm-sh/cpu-sh3/dma.h
include/asm-sh/cpu-sh3/gpio.h
include/asm-sh/cpu-sh3/mmu_context.h
include/asm-sh/cpu-sh3/timer.h
include/asm-sh/cpu-sh3/ubc.h
include/asm-sh/processor.h

index 538631ca10a68285f69177c84f6a6def3de1fad7..d2f557719489d692dec98ce2e3efea520e1fa2eb 100644 (file)
@@ -214,6 +214,13 @@ config CPU_SUBTYPE_SH7720
        help
          Select SH7720 if you have a SH3-DSP SH7720 CPU.
 
+config CPU_SUBTYPE_SH7721
+       bool "Support SH7721 processor"
+       select CPU_SH3
+       select CPU_HAS_DSP
+       help
+         Select SH7721 if you have a SH3-DSP SH7721 CPU.
+
 # SH-4 Processor Support
 
 config CPU_SUBTYPE_SH7750
index 2881d8471a17378af767cf81ed3b0336306b2f2d..dde00d5c24783be0ed2d00ba2eb82b57bd574dc2 100644 (file)
@@ -35,7 +35,7 @@ config EARLY_SCIF_CONSOLE_PORT
        default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
        default "0xf8420000" if CPU_SUBTYPE_SH7619
        default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
-       default "0xa4430000" if CPU_SUBTYPE_SH7720
+       default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
        default "0xffc30000" if CPU_SUBTYPE_SHX3
        default "0xffe80000" if CPU_SH4
        default "0x00000000"
index 4e711a0c3dae1925302ea3a368df888a0e946748..01936368b8b0d5529dfa6675a7b69560accfcbce 100644 (file)
@@ -12,7 +12,7 @@ config SH_DMA
 config NR_ONCHIP_DMA_CHANNELS
        int
        depends on SH_DMA
-       default "6" if CPU_SUBTYPE_SH7720
+       default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
        default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
        default "12" if CPU_SUBTYPE_SH7780
        default "4"
index 958bac1c585a9fe91fed90ee7cfdb8605cd3e857..5c3359756a926fe01e1107a1af4bfc53239b25e4 100644 (file)
@@ -25,6 +25,7 @@ static int dmte_irq_map[] = {
        DMTE2_IRQ,
        DMTE3_IRQ,
 #if defined(CONFIG_CPU_SUBTYPE_SH7720)  ||     \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)  ||     \
     defined(CONFIG_CPU_SUBTYPE_SH7751R) ||     \
     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||     \
     defined(CONFIG_CPU_SUBTYPE_SH7709)  ||     \
@@ -203,6 +204,7 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 }
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
     defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define dmaor_read_reg()       ctrl_inw(DMAOR)
 #define dmaor_write_reg(data)  ctrl_outw(data, DMAOR)
index 646eb6933614a0852ec21798e5d01265dbaac5ad..1afd05e62d1c26dc75aa8270db7ca5856c887f49 100644 (file)
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7709)      += setup-sh770x.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7710)       += setup-sh7710.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7712)       += setup-sh7710.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7720)       += setup-sh7720.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7721)       += setup-sh7720.o
 
 # Primary on-chip clocks (common)
 clock-$(CONFIG_CPU_SH3)                        := clock-sh3.o
index 22070e43e34d6e8801d311e435178e42fd67c6fb..fcc80bb7bee7f9de3192d6309554e1b9642848e5 100644 (file)
@@ -84,6 +84,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
                boot_cpu_data.type = CPU_SH7720;
 #endif
+#if defined(CONFIG_CPU_SUBTYPE_SH7721)
+               boot_cpu_data.type = CPU_SH7721;
+#endif
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
                boot_cpu_data.type = CPU_SH7705;
 
index a0929b8a95ae93de476d414613e5be22abb7b64d..00facd028a08ca8ba8fd5d8fdaa0add3bf5b5dc9 100644 (file)
@@ -127,8 +127,11 @@ static struct intc_vect vectors[] __initdata = {
        INTC_VECT(USBF_SPD, 0x6e0),   INTC_VECT(DMAC1_DEI0, 0x800),
        INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
        INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
-       INTC_VECT(SSL, 0x980),        INTC_VECT(USBFI0, 0xa20),
-       INTC_VECT(USBFI1, 0xa40),     INTC_VECT(USBHI, 0xa60),
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+       INTC_VECT(SSL, 0x980),
+#endif
+       INTC_VECT(USBFI0, 0xa20),     INTC_VECT(USBFI1, 0xa40),
+       INTC_VECT(USBHI, 0xa60),
        INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
        INTC_VECT(ADC, 0xbe0),        INTC_VECT(SCIF0, 0xc00),
        INTC_VECT(SCIF1, 0xc20),      INTC_VECT(PINT07, 0xc80),
@@ -168,7 +171,11 @@ static struct intc_prio_reg prio_registers[] __initdata = {
        { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
        { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
        { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
+#if defined(CONFIG_CPU_SUBTYPE_SH7720)
        { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
+#else
+       { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
+#endif
        { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
        { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
        { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
index 2f30977558adf9b11eb89b2dd3c3e8545c2abed7..957f256115434fa866ba16cd2f2bccc80664c23c 100644 (file)
@@ -63,7 +63,8 @@ static struct console bios_console = {
 #include <linux/serial_core.h>
 #include "../../../drivers/serial/sh-sci.h"
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define EPK_SCSMR_VALUE 0x000
 #define EPK_SCBRR_VALUE 0x00C
 #define EPK_FIFO_SIZE 64
@@ -117,7 +118,8 @@ static struct console scif_console = {
 };
 
 #if !defined(CONFIG_SH_STANDARD_BIOS)
-#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 static void scif_sercon_init(char *s)
 {
        sci_out(&scif_port, SCSCR, 0x0000);     /* clear TE and RE */
@@ -208,9 +210,11 @@ static int __init setup_early_printk(char *buf)
        if (!strncmp(buf, "serial", 6)) {
                early_console = &scif_console;
 
-#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \
-    !defined(CONFIG_SH_STANDARD_BIOS)
+#if !defined(CONFIG_SH_STANDARD_BIOS)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
                scif_sercon_init(buf + 6);
+#endif
 #endif
        }
 #endif
index 9c105c827e865a5cab178dae150a04703ef53460..48cd576754b5a2159f911e2dfa54f0f2e02ece84 100644 (file)
@@ -314,10 +314,10 @@ static const char *cpu_name[] = {
        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
-       [CPU_SH7729]    = "SH7729",     [CPU_SH7750]    = "SH7750",
-       [CPU_SH7750S]   = "SH7750S",    [CPU_SH7750R]   = "SH7750R",
-       [CPU_SH7751]    = "SH7751",     [CPU_SH7751R]   = "SH7751R",
-       [CPU_SH7760]    = "SH7760",
+       [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
+       [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
+       [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
+       [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
        [CPU_SH7770]    = "SH7770",     [CPU_SH7780]    = "SH7780",
        [CPU_SH7781]    = "SH7781",     [CPU_SH7343]    = "SH7343",
index 628ec9a15e383282a79df5b6701e35dd2122a56e..8935570008d2eb192d9d6698c2b4580ea3c0882c 100644 (file)
@@ -174,6 +174,7 @@ static int tmu_timer_init(void)
        tmu_timer_stop();
 
 #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
+    !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
     !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
     !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
     !defined(CONFIG_CPU_SUBTYPE_SHX3)
index 73440e26834beb8d09cd6b07edb0dd1e8b73208a..6fbfd140b7e714cb19776ccf721a2b8a159001a0 100644 (file)
@@ -302,7 +302,7 @@ static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
        }
        sci_out(port, SCFCR, fcr_val);
 }
-#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 {
        unsigned int fcr_val = 0;
index 0187dccfe8c1870d0ef9287b60d443e66a82d715..85562040a6d32445af4dfbc939fd11f14715dd0e 100644 (file)
@@ -46,7 +46,8 @@
  */
 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
 # define SCIF_ONLY
-#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7721)
 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
 # define SCIF_ONLY
 #define SCIF_ORER    0x0200   /* overrun error bit */
 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define SCIF_ORER    0x0200
 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 #define SCIF_RFDC_MASK 0x007f
 # define SCxSR_PER(port)               SCIF_PER
 # define SCxSR_BRK(port)               SCIF_BRK
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
          CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7720)
+      defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define SCIF_FNS(name, scif_offset, scif_size) \
   CPU_SCIF_FNS(name, scif_offset, scif_size)
 #else
 #endif
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 
 SCIF_FNS(SCSMR,  0x00, 16)
 SCIF_FNS(SCBRR,  0x04,  8)
@@ -512,7 +517,8 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port)
                return;
        }
 }
-#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7721)
 static inline int sci_rxd_in(struct uart_port *port)
 {
        if (port->mapbase == 0xa4430000)
@@ -696,7 +702,8 @@ static inline int sci_rxd_in(struct uart_port *port)
     defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7720)
+      defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
index 77dd45d8241490a0bf3ced9fd0107dff21afcc75..56bd838b7db4b692ccc3acc580745d048b5a2f66 100644 (file)
@@ -33,7 +33,8 @@
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
     defined(CONFIG_CPU_SUBTYPE_SH7710) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define CCR3   0xa40000b4
 #define CCR_CACHE_16KB  0x00010000
 #define CCR_CACHE_32KB 0x00020000
index 54bfece328c2724df33f44cf52e44ff8d96adc93..092ff9d872c3e6cf352236e82e32466c116defb6 100644 (file)
@@ -2,7 +2,9 @@
 #define __ASM_CPU_SH3_DMA_H
 
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define SH_DMAC_BASE   0xa4010020
 
 #define DMTE0_IRQ      48
index 48770c1c7bdffb561323b1cdbf63def20119c3a8..4e53eb314b8fc9b9b4c6584fda2f290c9353dc56 100644 (file)
@@ -12,7 +12,8 @@
 #ifndef _CPU_SH3_GPIO_H
 #define _CPU_SH3_GPIO_H
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7720)
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 
 /* Control registers */
 #define PORT_PACR      0xA4050100UL
index 16c2d63b7e39ef7b392eb7662739a1aef7791cc6..ab09da73ce770b5601c4a4c85a02235491450f88 100644 (file)
@@ -33,7 +33,8 @@
     defined(CONFIG_CPU_SUBTYPE_SH7709) || \
     defined(CONFIG_CPU_SUBTYPE_SH7710) || \
     defined(CONFIG_CPU_SUBTYPE_SH7712) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define INTEVT 0xa4000000      /* INTEVTE2(0xa4000000) */
 #else
 #define INTEVT 0xffffffd8
index 7b795ac5477cb215fd5958be2bab51f43ad49b7f..793acf12aa086e7b9124de5d735e446612baa536 100644 (file)
  * ---------------------------------------------------------------------------
  */
 
-#if  !defined(CONFIG_CPU_SUBTYPE_SH7720)
+#if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define TMU_TOCR       0xfffffe90      /* Byte access */
 #endif
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define TMU_012_TSTR   0xa412fe92      /* Byte access */
 
 #define TMU0_TCOR      0xa412fe94      /* Long access */
@@ -57,7 +58,7 @@
 #define TMU2_TCOR      0xfffffeac      /* Long access */
 #define TMU2_TCNT      0xfffffeb0      /* Long access */
 #define TMU2_TCR       0xfffffeb4      /* Word access */
-#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
+#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define TMU2_TCPR2     0xfffffeb8      /* Long access */
 #endif
 #endif
index 18467c574534aebf55d65d03c9756d368219057d..4e6381d5ff7a9ff909b580c9f130706c0bcae97e 100644 (file)
@@ -12,7 +12,8 @@
 #define __ASM_CPU_SH3_UBC_H
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720)
+    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7721)
 #define UBC_BARA               0xa4ffffb0
 #define UBC_BAMRA              0xa4ffffb4
 #define UBC_BBRA               0xa4ffffb8
index bbbdaab8de5f10bb97a8633897e8c9c0b60d38ff..f4a8da71ba45420dbd9c2767d0d7c91fc32061c2 100644 (file)
@@ -23,7 +23,7 @@ enum cpu_type {
        CPU_SH7705, CPU_SH7706, CPU_SH7707,
        CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
        CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
-       CPU_SH7720, CPU_SH7729,
+       CPU_SH7720, CPU_SH7721, CPU_SH7729,
 
        /* SH-4 types */
        CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,