Appearently, a big delay ~300ms is required before hw is settled and ready
to transfer samples on some hardware variants. Also, return back
"clocking to 48000Hz" message when something fails.
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
if (pos == 0) {
snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
__retry:
- if (attempt < 2) {
+ if (attempt < 3) {
+ msleep(300);
attempt++;
goto __again;
}
- return;
+ goto __end;
}
pos /= 4;
else if (pos < 47500 || pos > 48500)
/* not 48000Hz, tuning the clock.. */
chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
+ __end:
printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
}