MIPS: Fix core number detection for MT cores

In cores which implement the MT ASE, the CPUNum in the EBase register is
a concatenation of the core number & the VPE ID within that core. In
order to retrieve the correct core number CPUNum must be shifted
appropriately to remove the VPE ID bits.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bd712c91f48b6590f46ad27184c7eafe1a7e5c7f..6e8fb85ce7c3b076fd6bec6b2b770ed3b425c597 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,6 +23,7 @@
 #include <asm/cpu-type.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
 #include <asm/msa.h>
 #include <asm/watch.h>
 #include <asm/elf.h>
@@ -421,8 +422,11 @@ static void decode_configs(struct cpuinfo_mips *c)
        mips_probe_watch_registers(c);
 
 #ifndef CONFIG_MIPS_CPS
-       if (cpu_has_mips_r2)
+       if (cpu_has_mips_r2) {
                c->core = read_c0_ebase() & 0x3ff;
+               if (cpu_has_mipsmt)
+                       c->core >>= fls(core_nvpes()) - 1;
+       }
 #endif
 }