SPEAr: Add DT bindings for SPEAr's timer
authorViresh Kumar <viresh.kumar@st.com>
Sat, 21 Apr 2012 07:45:37 +0000 (13:15 +0530)
committerArnd Bergmann <arnd@arndb.de>
Sat, 12 May 2012 19:03:26 +0000 (21:03 +0200)
All SPEAr SoC's use ST's Timer module. This patch adds device tree probing
capability for that.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
12 files changed:
Documentation/devicetree/bindings/arm/spear-timer.txt [new file with mode: 0644]
arch/arm/boot/dts/spear3xx.dtsi
arch/arm/boot/dts/spear600.dtsi
arch/arm/mach-spear3xx/include/mach/generic.h
arch/arm/mach-spear3xx/include/mach/irqs.h
arch/arm/mach-spear3xx/include/mach/spear.h
arch/arm/mach-spear3xx/spear3xx.c
arch/arm/mach-spear6xx/include/mach/generic.h
arch/arm/mach-spear6xx/include/mach/irqs.h
arch/arm/mach-spear6xx/include/mach/spear.h
arch/arm/mach-spear6xx/spear6xx.c
arch/arm/plat-spear/time.c

diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt
new file mode 100644 (file)
index 0000000..c001722
--- /dev/null
@@ -0,0 +1,18 @@
+* SPEAr ARM Timer
+
+** Timer node required properties:
+
+- compatible : Should be:
+       "st,spear-timer"
+- reg: Address range of the timer registers
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupt: Should contain the timer interrupt number
+
+Example:
+
+       timer@f0000000 {
+               compatible = "st,spear-timer";
+               reg = <0xf0000000 0x400>;
+               interrupts = <2>;
+       };
index 0ae7c8e86311ddc0950e11d97ad487a40d1542a2..91072553963f02566caf2d6a42c727540998a162 100644 (file)
                                interrupts = <12>;
                                status = "disabled";
                        };
+
+                       timer@f0000000 {
+                               compatible = "st,spear-timer";
+                               reg = <0xf0000000 0x400>;
+                               interrupts = <2>;
+                       };
                };
        };
 };
index d777e3a6f178dee9bfba070d1850e47f4da2c507..089f0a42c50ef4244765efc59450011637e33a08 100644 (file)
                                interrupts = <28>;
                                status = "disabled";
                        };
+
+                       timer@f0000000 {
+                               compatible = "st,spear-timer";
+                               reg = <0xf0000000 0x400>;
+                               interrupts = <16>;
+                       };
                };
        };
 };
index e4f4d721cda2c909e075448a33e052374cb08015..efb69357429ac926124e737097f5247ed03a6e9f 100644 (file)
@@ -28,7 +28,7 @@ extern struct pl022_ssp_controller pl022_plat_data;
 extern struct pl08x_platform_data pl080_plat_data;
 
 /* Add spear3xx family function declarations here */
-void __init spear_setup_timer(resource_size_t base, int irq);
+void __init spear_setup_of_timer(void);
 void __init spear3xx_map_io(void);
 void __init spear3xx_dt_init_irq(void);
 
index 319620a1afb4ea517654c7861caaac8668566bc0..51bd62a0254c814acca905b44696e834700c9cb2 100644 (file)
@@ -16,7 +16,6 @@
 
 /* FIXME: probe all these from DT */
 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM          1
-#define SPEAR3XX_IRQ_CPU_GPT1_1                        2
 #define SPEAR3XX_IRQ_GEN_RAS_1                 28
 #define SPEAR3XX_IRQ_GEN_RAS_2                 29
 #define SPEAR3XX_IRQ_GEN_RAS_3                 30
index 6d4dadc67633bd119602839d5ac502de0afab79c..04da906b0d4cb1e462af391bd41ce68245acbabe 100644 (file)
@@ -26,7 +26,6 @@
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE       UL(0xF0000000)
 #define VA_SPEAR6XX_ML_CPU_BASE                UL(0xF0000000)
-#define SPEAR3XX_CPU_TMR_BASE          UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE    UL(0xFC000000)
index bbb11efa6056ff1845648027e18fd29a46f9278d..25c6c67d5b07c813bb5a1e75b7d3e0ed6e74299c 100644 (file)
@@ -534,7 +534,7 @@ static void __init spear3xx_timer_init(void)
        clk_put(gpt_clk);
        clk_put(pclk);
 
-       spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1);
+       spear_setup_of_timer();
 }
 
 struct sys_timer spear3xx_timer = {
index 7167fd331d86e8e6a05546e7d1ecb3dd4774f94f..65514b159370d909a89a2b9fc9d36897cb4f28f1 100644 (file)
@@ -16,7 +16,7 @@
 
 #include <linux/init.h>
 
-void __init spear_setup_timer(resource_size_t base, int irq);
+void __init spear_setup_of_timer(void);
 void spear_restart(char, const char *);
 void __init spear6xx_clk_init(void);
 
index 2b735389e74b341c76bd75f8a140ae8bc7163cf3..37a5c411a8665808fc910acac2811f05486068c6 100644 (file)
@@ -16,9 +16,6 @@
 
 /* IRQ definitions */
 /* VIC 1 */
-/* FIXME: probe this from DT */
-#define IRQ_CPU_GPT1_1                         16
-
 #define IRQ_VIC_END                            64
 
 /* GPIO pins virtual irqs */
index d278ed047a53024b0da18e0c09ce029034b6e60b..cb8ed2f4dc85fd5db84df13fceb674664304c6cf 100644 (file)
@@ -25,7 +25,6 @@
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE           UL(0xF0000000)
 #define VA_SPEAR6XX_ML_CPU_BASE                UL(0xF0000000)
-#define SPEAR6XX_CPU_TMR_BASE          UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE    UL(0xFC000000)
index de194dbb83715803887309dad8c2377db2a1a4ca..7ae4d5be6cb5d58ba5ff66564aa53ed5ce3bc190 100644 (file)
@@ -448,7 +448,7 @@ static void __init spear6xx_timer_init(void)
        clk_put(gpt_clk);
        clk_put(pclk);
 
-       spear_setup_timer(SPEAR6XX_CPU_TMR_BASE, IRQ_CPU_GPT1_1);
+       spear_setup_of_timer();
 }
 
 struct sys_timer spear6xx_timer = {
index a3164d1647fda73bb905d746336d0493b748dffb..9a378987bbb186ca7cebb4aa587fe3695551720a 100644 (file)
@@ -18,6 +18,8 @@
 #include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
@@ -197,19 +199,32 @@ static void __init spear_clockevent_init(int irq)
        setup_irq(irq, &spear_timer_irq);
 }
 
-void __init spear_setup_timer(resource_size_t base, int irq)
+const static struct of_device_id timer_of_match[] __initconst = {
+       { .compatible = "st,spear-timer", },
+       { },
+};
+
+void __init spear_setup_of_timer(void)
 {
-       int ret;
+       struct device_node *np;
+       int irq, ret;
+
+       np = of_find_matching_node(NULL, timer_of_match);
+       if (!np) {
+               pr_err("%s: No timer passed via DT\n", __func__);
+               return;
+       }
 
-       if (!request_mem_region(base, SZ_1K, "gpt0")) {
-               pr_err("%s:cannot get IO addr\n", __func__);
+       irq = irq_of_parse_and_map(np, 0);
+       if (!irq) {
+               pr_err("%s: No irq passed for timer via DT\n", __func__);
                return;
        }
 
-       gpt_base = ioremap(base, SZ_1K);
+       gpt_base = of_iomap(np, 0);
        if (!gpt_base) {
-               pr_err("%s:ioremap failed for gpt\n", __func__);
-               goto err_mem;
+               pr_err("%s: of iomap failed\n", __func__);
+               return;
        }
 
        gpt_clk = clk_get_sys("gpt0", NULL);
@@ -233,6 +248,4 @@ err_clk:
        clk_put(gpt_clk);
 err_iomap:
        iounmap(gpt_base);
-err_mem:
-       release_mem_region(base, SZ_1K);
 }