[9610] fimc-is2: added pafstat_rdma sfr settings
authorEunyoung Lee <ey470.lee@samsung.com>
Fri, 9 Feb 2018 08:12:03 +0000 (17:12 +0900)
committerEunyoung Lee <ey470.lee@samsung.com>
Tue, 19 Jun 2018 08:47:05 +0000 (17:47 +0900)
Change-Id: I0bce90312b4c98088a1f92a8553f82ba27d78f28
Signed-off-by: Eunyoung Lee <ey470.lee@samsung.com>
drivers/media/platform/exynos/fimc-is2/sensor/module_framework/pafstat/fimc-is-hw-pafstat-v1_0.c
drivers/media/platform/exynos/fimc-is2/sensor/module_framework/pafstat/fimc-is-hw-pafstat-v1_0.h
drivers/media/platform/exynos/fimc-is2/sensor/module_framework/pafstat/fimc-is-hw-pafstat.h
drivers/media/platform/exynos/fimc-is2/sensor/module_framework/pafstat/fimc-is-pafstat.c

index 8ce6cfcdd823cdf1e5bbbfd498730b8748dae917..2d47d32af0435259aa4c5143c5f05f0e3ac137a9 100644 (file)
@@ -114,6 +114,9 @@ void pafstat_hw_s_input_path(void __iomem *base_reg, enum pafstat_input_path inp
 {
        u32 value = (input == PAFSTAT_INPUT_DMA ? 1 : 0);
 
+       fimc_is_hw_set_field(base_reg, &pafstat_regs[PAFSTAT_R_CTX_SEL_OTF],
+                       &pafstat_fields[PAFSTAT_F_CTX_SEL_OTF], input);
+
        fimc_is_hw_set_field(base_reg, &pafstat_regs[PAFSTAT_R_CTX_LIC_IS_DMA],
                        &pafstat_fields[PAFSTAT_F_CTX_LIC_IS_DMA], value);
 }
@@ -258,9 +261,129 @@ int pafstat_hw_sw_reset(void __iomem *base_reg)
        return 0;
 }
 
-/* RDMA */
-void pafstat_hw_s_rdma_reset(void __iomem *base_reg)
+/* PAF RDMA */
+void fimc_is_hw_paf_oneshot_enable(void __iomem *base_reg, int enable)
+{
+       pafstat_hw_s_ready(base_reg, 1);
+
+       fimc_is_hw_set_field(base_reg, &pafstat_regs[PAFSTAT_R_CTX_ONESHOT],
+                       &pafstat_fields[PAFSTAT_F_CTX_ONESHOT], 1);
+}
+
+void fimc_is_hw_paf_common_config(void __iomem *base_reg_com, void __iomem *base_reg, u32 paf_ch, u32 width, u32 height)
+{
+       int enable = 0;
+       enum pafstat_input_path input = PAFSTAT_INPUT_DMA;
+
+       /* PAFSTAT core setting */
+       enable = pafstat_hw_s_sensor_mode(base_reg, PD_NONE);
+       pafstat_hw_s_irq_mask(base_reg, PAFSTAT_INT_MASK);
+
+       pafstat_hw_s_img_size(base_reg, width, height);
+
+       pafstat_hw_s_input_path(base_reg, input);
+
+       pafstat_hw_s_timeout_cnt_clear(base_reg);
+}
+
+void fimc_is_hw_paf_rdma_reset(void __iomem *base_reg)
 {
+       int ret = 0;
+       u32 timeout = 1000;
+
        fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_COM_RESET],
                        &pafstat_rdma_fields[PAFSTAT_RDMA_F_COM_SW_RESET], 1);
+
+       do {
+               ret = fimc_is_hw_get_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_COM_RESET_STATUS],
+                               &pafstat_rdma_fields[PAFSTAT_RDMA_F_COM_SW_RESET_STATUS]);
+
+               if (ret == 0x1)
+                       break;
+
+               timeout--;
+       } while (timeout);
+
+       if (timeout == 0)
+               err("PAFSTAT RDMA reset fail\n");
+}
+
+void fimc_is_hw_paf_rdma_config(void __iomem *base_reg, u32 hw_format, u32 bitwidth, u32 width, u32 height)
+{
+       enum pafstat_rdma_format dma_format = PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN;
+       u32 stride_size;
+
+       switch (hw_format) {
+       case DMA_OUTPUT_FORMAT_BAYER_PACKED:
+               if (bitwidth == DMA_OUTPUT_BIT_WIDTH_10BIT)
+                       dma_format = PAFSTAT_RDMA_FORMAT_10BIT_PACK;
+               else if (bitwidth == DMA_OUTPUT_BIT_WIDTH_12BIT)
+                       dma_format = PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN;
+               break;
+       case DMA_OUTPUT_FORMAT_BAYER:
+               if (bitwidth == DMA_OUTPUT_BIT_WIDTH_8BIT)
+                       dma_format = PAFSTAT_RDMA_FORMAT_8BIT_PACK;
+               break;
+       default:
+               dma_format = PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN;
+               break;
+       }
+
+       /* same as CSIS WDMA align */
+       switch (dma_format) {
+       case PAFSTAT_RDMA_FORMAT_8BIT_PACK:
+               stride_size = round_up(width, DMA_OUTPUT_BIT_WIDTH_16BIT);
+               break;
+       case PAFSTAT_RDMA_FORMAT_10BIT_PACK:
+       case PAFSTAT_RDMA_FORMAT_ANDROID10:
+               stride_size = round_up((width * 5 / 4), DMA_OUTPUT_BIT_WIDTH_16BIT);
+               break;
+       case PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN:
+       case PAFSTAT_RDMA_FORMAT_12BIT_PACK_MSB_ALIGN:
+               stride_size = round_up((width * 3 / 2), DMA_OUTPUT_BIT_WIDTH_16BIT);
+               break;
+       case PAFSTAT_RDMA_FORMAT_16BIT_PACK_LSB_ALIGN:
+               stride_size = round_up((width * 2), DMA_OUTPUT_BIT_WIDTH_16BIT);
+               break;
+       default:
+               stride_size = round_up(width, DMA_OUTPUT_BIT_WIDTH_16BIT);
+               break;
+       }
+
+       fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_DATA_FORMAT],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_DATA_FORMAT], dma_format);
+
+       fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_IMG_WIDTH],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_IMG_WIDTH], width);
+       fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_IMG_HEIGHT],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_IMG_HEIGHT], height);
+
+       fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_IMG_STRIDE],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_IMG_STRIDE], stride_size);
 }
+
+void fimc_is_hw_paf_rdma_set_addr(void __iomem *base_reg, u32 addr)
+{
+       fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_BASE_ADDR],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_BASE_ADDR], addr);
+}
+
+void fimc_is_hw_paf_rdma_enable(void __iomem *base_reg_com, void __iomem *base_reg, u32 enable)
+{
+       fimc_is_hw_set_field(base_reg_com, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_COM_QACTIVE],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_COM_RDMA_QACTIVE], enable);
+       fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_EN],
+                       &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_EN], enable);
+}
+
+void fimc_is_hw_paf_sfr_dump(void __iomem *base_reg_com, void __iomem *base_reg)
+{
+       info("pafstat sfr dump\n");
+
+       info("PAFSTAT SFR DUMP : %p\n", base_reg_com);
+       fimc_is_hw_dump_regs(base_reg_com, pafstat_regs, PAFSTAT_R_PAFSTAT_YEXTR_HDRMODE);
+
+       info("PAFSTAT RDMA SFR DUMP : %p\n", base_reg);
+       fimc_is_hw_dump_regs(base_reg, pafstat_rdma_regs, PAFSTAT_RDMA_REG_CNT);
+}
+
index 9c83e10d2e140e9046e45453c7a243411f6749e8..a4d98b61db50ee82a017318c10ac2ad920bdb9d9 100644 (file)
 #define PAFSTAT_STATIC_MAXHEIGHT       15
 #define PAFSTAT_STATIC_ELEMENT_SIZE    448
 
+enum pafstat_rdma_format {
+       /*
+        * RDAM data format.
+        * 0 : 8bit
+        * 1 : 10bit
+        * 2 : 12bit {00, 10bit}
+        * 3 : 12bit {10bit, 00}
+        * 4 : 16bit {000000, 10bit}
+        * 5 : Android10
+        */
+       PAFSTAT_RDMA_FORMAT_8BIT_PACK = 0,
+       PAFSTAT_RDMA_FORMAT_10BIT_PACK,
+       PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN,
+       PAFSTAT_RDMA_FORMAT_12BIT_PACK_MSB_ALIGN,
+       PAFSTAT_RDMA_FORMAT_16BIT_PACK_LSB_ALIGN,
+       PAFSTAT_RDMA_FORMAT_ANDROID10,
+};
+
 /* the total count of PAFSTAT v1.0's regs */
 enum fimc_is_hw_pafstat_reg_name {
        /* common between context0 and context1 */
index 1de2e1a268964608cd12b7541c663b36125cad32..fa86f1391e1002a6c344e809ecf458404ac47aca 100644 (file)
@@ -89,6 +89,14 @@ void pafstat_hw_s_timeout_cnt_clear(void __iomem *base_reg);
 void pafstat_hw_s_intr_mask_all_context(void);
 int pafstat_hw_sw_reset(void __iomem *base_reg);
 
-/* RDMA */
-void pafstat_hw_s_rdma_reset(void __iomem *base_reg);
+/* PAF RDMA */
+void fimc_is_hw_paf_common_config(void __iomem *base_reg_com, void __iomem *base_reg,
+       u32 paf_ch, u32 width, u32 height);
+void fimc_is_hw_paf_rdma_reset(void __iomem *base_reg);
+void fimc_is_hw_paf_rdma_config(void __iomem *base_reg, u32 hw_format, u32 bitwidth, u32 width, u32 height);
+void fimc_is_hw_paf_rdma_set_addr(void __iomem *base_reg, u32 addr);
+void fimc_is_hw_paf_rdma_enable(void __iomem *base_reg_com, void __iomem *base_reg, u32 enable);
+void fimc_is_hw_paf_sfr_dump(void __iomem *base_reg_com, void __iomem *base_reg);
+void fimc_is_hw_paf_oneshot_enable(void __iomem *base_reg, int enable);
+
 #endif
index 70c971bbe1ac9d4c3d0c6bcc83a030a377b05b7c..e00d9fdc652fae7f4bb068d34841fb3d44eb92fa 100644 (file)
@@ -374,6 +374,7 @@ static int pafstat_s_stream(struct v4l2_subdev *subdev, int pd_mode)
        pafstat_hw_com_s_lic_mode(pafstat->regs_com, pafstat->id, lic_mode, input);
        pafstat_hw_com_s_output_mask(pafstat->regs_com, 0);
        pafstat_hw_s_input_path(pafstat->regs, input);
+       pafstat_hw_s_img_size(pafstat->regs, pafstat->in_width, pafstat->in_height);
 
        pafstat_hw_s_ready(pafstat->regs, 1);
        pafstat_hw_s_enable(pafstat->regs, 1);
@@ -484,7 +485,7 @@ static const struct v4l2_subdev_ops subdev_ops = {
 struct fimc_is_paf_ops pafstat_ops = {
        .set_param = pafstat_hw_set_regs,
        .get_ready = pafstat_hw_get_ready,
-       .set_num_buffers = pafstat_set_num_buffers
+       .set_num_buffers = pafstat_set_num_buffers,
 };
 
 static int __init pafstat_probe(struct platform_device *pdev)