{
u32 value = (input == PAFSTAT_INPUT_DMA ? 1 : 0);
+ fimc_is_hw_set_field(base_reg, &pafstat_regs[PAFSTAT_R_CTX_SEL_OTF],
+ &pafstat_fields[PAFSTAT_F_CTX_SEL_OTF], input);
+
fimc_is_hw_set_field(base_reg, &pafstat_regs[PAFSTAT_R_CTX_LIC_IS_DMA],
&pafstat_fields[PAFSTAT_F_CTX_LIC_IS_DMA], value);
}
return 0;
}
-/* RDMA */
-void pafstat_hw_s_rdma_reset(void __iomem *base_reg)
+/* PAF RDMA */
+void fimc_is_hw_paf_oneshot_enable(void __iomem *base_reg, int enable)
+{
+ pafstat_hw_s_ready(base_reg, 1);
+
+ fimc_is_hw_set_field(base_reg, &pafstat_regs[PAFSTAT_R_CTX_ONESHOT],
+ &pafstat_fields[PAFSTAT_F_CTX_ONESHOT], 1);
+}
+
+void fimc_is_hw_paf_common_config(void __iomem *base_reg_com, void __iomem *base_reg, u32 paf_ch, u32 width, u32 height)
+{
+ int enable = 0;
+ enum pafstat_input_path input = PAFSTAT_INPUT_DMA;
+
+ /* PAFSTAT core setting */
+ enable = pafstat_hw_s_sensor_mode(base_reg, PD_NONE);
+ pafstat_hw_s_irq_mask(base_reg, PAFSTAT_INT_MASK);
+
+ pafstat_hw_s_img_size(base_reg, width, height);
+
+ pafstat_hw_s_input_path(base_reg, input);
+
+ pafstat_hw_s_timeout_cnt_clear(base_reg);
+}
+
+void fimc_is_hw_paf_rdma_reset(void __iomem *base_reg)
{
+ int ret = 0;
+ u32 timeout = 1000;
+
fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_COM_RESET],
&pafstat_rdma_fields[PAFSTAT_RDMA_F_COM_SW_RESET], 1);
+
+ do {
+ ret = fimc_is_hw_get_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_COM_RESET_STATUS],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_COM_SW_RESET_STATUS]);
+
+ if (ret == 0x1)
+ break;
+
+ timeout--;
+ } while (timeout);
+
+ if (timeout == 0)
+ err("PAFSTAT RDMA reset fail\n");
+}
+
+void fimc_is_hw_paf_rdma_config(void __iomem *base_reg, u32 hw_format, u32 bitwidth, u32 width, u32 height)
+{
+ enum pafstat_rdma_format dma_format = PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN;
+ u32 stride_size;
+
+ switch (hw_format) {
+ case DMA_OUTPUT_FORMAT_BAYER_PACKED:
+ if (bitwidth == DMA_OUTPUT_BIT_WIDTH_10BIT)
+ dma_format = PAFSTAT_RDMA_FORMAT_10BIT_PACK;
+ else if (bitwidth == DMA_OUTPUT_BIT_WIDTH_12BIT)
+ dma_format = PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN;
+ break;
+ case DMA_OUTPUT_FORMAT_BAYER:
+ if (bitwidth == DMA_OUTPUT_BIT_WIDTH_8BIT)
+ dma_format = PAFSTAT_RDMA_FORMAT_8BIT_PACK;
+ break;
+ default:
+ dma_format = PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN;
+ break;
+ }
+
+ /* same as CSIS WDMA align */
+ switch (dma_format) {
+ case PAFSTAT_RDMA_FORMAT_8BIT_PACK:
+ stride_size = round_up(width, DMA_OUTPUT_BIT_WIDTH_16BIT);
+ break;
+ case PAFSTAT_RDMA_FORMAT_10BIT_PACK:
+ case PAFSTAT_RDMA_FORMAT_ANDROID10:
+ stride_size = round_up((width * 5 / 4), DMA_OUTPUT_BIT_WIDTH_16BIT);
+ break;
+ case PAFSTAT_RDMA_FORMAT_12BIT_PACK_LSB_ALIGN:
+ case PAFSTAT_RDMA_FORMAT_12BIT_PACK_MSB_ALIGN:
+ stride_size = round_up((width * 3 / 2), DMA_OUTPUT_BIT_WIDTH_16BIT);
+ break;
+ case PAFSTAT_RDMA_FORMAT_16BIT_PACK_LSB_ALIGN:
+ stride_size = round_up((width * 2), DMA_OUTPUT_BIT_WIDTH_16BIT);
+ break;
+ default:
+ stride_size = round_up(width, DMA_OUTPUT_BIT_WIDTH_16BIT);
+ break;
+ }
+
+ fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_DATA_FORMAT],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_DATA_FORMAT], dma_format);
+
+ fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_IMG_WIDTH],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_IMG_WIDTH], width);
+ fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_IMG_HEIGHT],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_IMG_HEIGHT], height);
+
+ fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_IMG_STRIDE],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_IMG_STRIDE], stride_size);
}
+
+void fimc_is_hw_paf_rdma_set_addr(void __iomem *base_reg, u32 addr)
+{
+ fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_BASE_ADDR],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_BASE_ADDR], addr);
+}
+
+void fimc_is_hw_paf_rdma_enable(void __iomem *base_reg_com, void __iomem *base_reg, u32 enable)
+{
+ fimc_is_hw_set_field(base_reg_com, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_COM_QACTIVE],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_COM_RDMA_QACTIVE], enable);
+ fimc_is_hw_set_field(base_reg, &pafstat_rdma_regs[PAFSTAT_RDMA_R_RDMA_I_EN],
+ &pafstat_rdma_fields[PAFSTAT_RDMA_F_RDMA_I_EN], enable);
+}
+
+void fimc_is_hw_paf_sfr_dump(void __iomem *base_reg_com, void __iomem *base_reg)
+{
+ info("pafstat sfr dump\n");
+
+ info("PAFSTAT SFR DUMP : %p\n", base_reg_com);
+ fimc_is_hw_dump_regs(base_reg_com, pafstat_regs, PAFSTAT_R_PAFSTAT_YEXTR_HDRMODE);
+
+ info("PAFSTAT RDMA SFR DUMP : %p\n", base_reg);
+ fimc_is_hw_dump_regs(base_reg, pafstat_rdma_regs, PAFSTAT_RDMA_REG_CNT);
+}
+