mtd: nand: sunxi: fix clk rate calculation

Unlike what is specified in the Allwinner datasheets, the NAND clock rate
is not equal to 2/T but 1/T. Fix the clock rate selection accordingly.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>

diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 546a9cae9bd11f213990a3d01f39886b85fc37f7..05b33035f6510263d207cc36d272ce847355841d 100644 (file)
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1208,12 +1208,12 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
        min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
 
        /*
-        * Convert min_clk_period into a clk frequency, then get the
-        * appropriate rate for the NAND controller IP given this formula
-        * (specified in the datasheet):
-        * nand clk_rate = 2 * min_clk_rate
+        * Unlike what is stated in Allwinner datasheet, the clk_rate should
+        * be set to (1 / min_clk_period), and not (2 / min_clk_period).
+        * This new formula was verified with a scope and validated by
+        * Allwinner engineers.
         */
-       chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
+       chip->clk_rate = NSEC_PER_SEC / min_clk_period;
 
        return 0;
 }