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clk: ux500: Update sdmmc clock to 100MHz for u8500
author
Ulf Hansson
<ulf.hansson@linaro.org>
Mon, 24 Sep 2012 14:43:19 +0000
(16:43 +0200)
committer
Mike Turquette
<mturquette@linaro.org>
Mon, 29 Oct 2012 18:06:07 +0000
(11:06 -0700)
For u8500 and using 100MHz as the frequency also requires the ape opp 100
voltage, thus use the prcmu_opp_volt_scalable clock type.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/ux500/u8500_clk.c
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diff --git
a/drivers/clk/ux500/u8500_clk.c
b/drivers/clk/ux500/u8500_clk.c
index ca4a25ed844c379315c2834dcd239c4b9d50940d..7bebf1f62c65d6d752c47fb1d12ab649a39875d4 100644
(file)
--- a/
drivers/clk/ux500/u8500_clk.c
+++ b/
drivers/clk/ux500/u8500_clk.c
@@
-170,10
+170,11
@@
void u8500_clk_init(void)
clk_register_clkdev(clk, NULL, "mtu0");
clk_register_clkdev(clk, NULL, "mtu1");
- clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
+ clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
+ 100000000,
+ CLK_IS_ROOT|CLK_SET_RATE_GATE);
clk_register_clkdev(clk, NULL, "sdmmc");
-
clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
clk_register_clkdev(clk, "dsihs2", "mcde");