ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsi

The A80 has 4 mmc controllers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index 1925c89ee701ff8825df2e7069c30a5590c39339..7387fb2a51116cf289c29ccbe2c822c0a521b751 100644 (file)
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -333,6 +333,54 @@
                 */
                ranges = <0 0 0 0x20000000>;
 
+               mmc0: mmc@01c0f000 {
+                       compatible = "allwinner,sun5i-a13-mmc";
+                       reg = <0x01c0f000 0x1000>;
+                       clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
+                                <&mmc0_clk 1>, <&mmc0_clk 2>;
+                       clock-names = "ahb", "mmc", "output", "sample";
+                       resets = <&mmc_config_clk 0>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               mmc1: mmc@01c10000 {
+                       compatible = "allwinner,sun5i-a13-mmc";
+                       reg = <0x01c10000 0x1000>;
+                       clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
+                                <&mmc1_clk 1>, <&mmc1_clk 2>;
+                       clock-names = "ahb", "mmc", "output", "sample";
+                       resets = <&mmc_config_clk 1>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               mmc2: mmc@01c11000 {
+                       compatible = "allwinner,sun5i-a13-mmc";
+                       reg = <0x01c11000 0x1000>;
+                       clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
+                                <&mmc2_clk 1>, <&mmc2_clk 2>;
+                       clock-names = "ahb", "mmc", "output", "sample";
+                       resets = <&mmc_config_clk 2>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               mmc3: mmc@01c12000 {
+                       compatible = "allwinner,sun5i-a13-mmc";
+                       reg = <0x01c12000 0x1000>;
+                       clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
+                                <&mmc3_clk 1>, <&mmc3_clk 2>;
+                       clock-names = "ahb", "mmc", "output", "sample";
+                       resets = <&mmc_config_clk 3>;
+                       reset-names = "ahb";
+                       interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
                mmc_config_clk: clk@01c13000 {
                        compatible = "allwinner,sun9i-a80-mmc-config-clk";
                        reg = <0x01c13000 0x10>;