OMAP3 clock: initialize SDRC timings at kernel start

On the OMAP3, initialize SDRC timings when the kernel boots.  This ensures
that the kernel is running with known, optimized SDRC timings, rather than
whatever was configured by the bootloader.

Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 9e43fe5209d337b7f149099d469339d670b572e6..5458ab3bf65a69df311ff1ec387f4d93591f6093 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -718,9 +718,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (clk != &dpll3_m2_ck)
                return -EINVAL;
 
-       if (rate == clk->rate)
-               return 0;
-
        validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
        if (validrate != rate)
                return -EINVAL;

diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 32afd944821625b4d49b9654573a9b72719c0430..3a86b0f660314c28234c31fe7bd1e731d1a6b95e 100644 (file)
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 
 #include <asm/tlb.h>
 
@@ -241,6 +242,40 @@ void __init omap2_map_common_io(void)
        omapfb_reserve_sdram();
 }
 
+/*
+ * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
+ *
+ * Sets the CORE DPLL3 M2 divider to the same value that it's at
+ * currently.  This has the effect of setting the SDRC SDRAM AC timing
+ * registers to the values currently defined by the kernel.  Currently
+ * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
+ * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
+ * or passes along the return value of clk_set_rate().
+ */
+static int __init _omap2_init_reprogram_sdrc(void)
+{
+       struct clk *dpll3_m2_ck;
+       int v = -EINVAL;
+       long rate;
+
+       if (!cpu_is_omap34xx())
+               return 0;
+
+       dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
+       if (!dpll3_m2_ck)
+               return -EINVAL;
+
+       rate = clk_get_rate(dpll3_m2_ck);
+       pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
+       v = clk_set_rate(dpll3_m2_ck, rate);
+       if (v)
+               pr_err("dpll3_m2_clk rate change failed: %d\n", v);
+
+       clk_put(dpll3_m2_ck);
+
+       return v;
+}
+
 void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
 {
        omap2_mux_init();
@@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
        clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
        omap2_clk_init();
        omap2_sdrc_init(sp);
+       _omap2_init_reprogram_sdrc();
 #endif
        gpmc_init();
 }