dispc_write_reg(DISPC_IRQSTATUS, mask);
}
-static u32 dispc_read_irqenable(void)
-{
- return dispc_read_reg(DISPC_IRQENABLE);
-}
-
static void dispc_write_irqenable(u32 mask)
{
u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
dispc_clear_irqstatus((mask ^ old_mask) & mask);
dispc_write_reg(DISPC_IRQENABLE, mask);
+
+ /* flush posted write */
+ dispc_read_reg(DISPC_IRQENABLE);
}
void dispc_enable_sidle(void)
static const struct dispc_ops dispc_ops = {
.read_irqstatus = dispc_read_irqstatus,
.clear_irqstatus = dispc_clear_irqstatus,
- .read_irqenable = dispc_read_irqenable,
.write_irqenable = dispc_write_irqenable,
.request_irq = dispc_request_irq,
struct dispc_ops {
u32 (*read_irqstatus)(void);
void (*clear_irqstatus)(u32 mask);
- u32 (*read_irqenable)(void);
void (*write_irqenable)(u32 mask);
int (*request_irq)(irq_handler_t handler, void *dev_id);
DBG("irqmask=%08x", irqmask);
priv->dispc_ops->write_irqenable(irqmask);
- priv->dispc_ops->read_irqenable(); /* flush posted write */
}
static void omap_irq_wait_handler(struct omap_irq_wait *wait)