/* get chipcommon chipstatus */
if (sii->pub.ccrev >= 11)
- sii->pub.chipst = R_REG(&cc->chipstatus);
+ sii->chipst = R_REG(&cc->chipstatus);
/* get chipcommon capabilites */
sii->pub.cccaps = R_REG(&cc->capabilities);
/* figure out bus/orignal core idx */
sii->pub.buscoretype = NODEV_CORE_ID;
sii->pub.buscorerev = NOREV;
- sii->pub.buscoreidx = BADIDX;
+ sii->buscoreidx = BADIDX;
pci = pcie = false;
pcirev = pcierev = NOREV;
if (pci) {
sii->pub.buscoretype = PCI_CORE_ID;
sii->pub.buscorerev = pcirev;
- sii->pub.buscoreidx = pciidx;
+ sii->buscoreidx = pciidx;
} else if (pcie) {
sii->pub.buscoretype = PCIE_CORE_ID;
sii->pub.buscorerev = pcierev;
- sii->pub.buscoreidx = pcieidx;
+ sii->buscoreidx = pcieidx;
}
/* fixup necessary chip/core configurations */
savewin = 0;
- sih->buscoreidx = BADIDX;
+ sii->buscoreidx = BADIDX;
sii->curmap = regs;
sii->pbus = pbus;
fast = true;
r = (u32 __iomem *)((__iomem char *)sii->curmap +
PCI_16KB0_CCREGS_OFFSET + regoff);
- } else if (sii->pub.buscoreidx == coreidx) {
+ } else if (sii->buscoreidx == coreidx) {
/*
* pci registers are at either in the last 2KB of
* an 8KB window or, in pcie and pci rev 13 at 8KB
siflag = ai_flag(sih);
/* switch over to pci core */
- regs = ai_setcoreidx(sih, sii->pub.buscoreidx);
+ regs = ai_setcoreidx(sih, sii->buscoreidx);
}
/*
bool ai_is_sprom_available(struct si_pub *sih)
{
+ struct si_info *sii = (struct si_info *)sih;
+
if (sih->ccrev >= 31) {
- struct si_info *sii;
uint origidx;
struct chipcregs __iomem *cc;
u32 sromctrl;
if ((sih->cccaps & CC_CAP_SROM) == 0)
return false;
- sii = (struct si_info *)sih;
origidx = sii->curidx;
cc = ai_setcoreidx(sih, SI_CC_IDX);
sromctrl = R_REG(&cc->sromcontrol);
switch (sih->chip) {
case BCM4313_CHIP_ID:
- return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
+ return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
default:
return true;
}
bool ai_is_otp_disabled(struct si_pub *sih)
{
+ struct si_info *sii = (struct si_info *)sih;
+
switch (sih->chip) {
case BCM4313_CHIP_ID:
- return (sih->chipst & CST4313_OTP_PRESENT) == 0;
+ return (sii->chipst & CST4313_OTP_PRESENT) == 0;
/* These chips always have their OTP on */
case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID:
struct si_pub {
uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
uint buscorerev; /* buscore rev */
- uint buscoreidx; /* buscore index */
int ccrev; /* chip common core rev */
u32 cccaps; /* chip common capabilities */
int pmurev; /* pmu core rev */
uint chip; /* chip number */
uint chiprev; /* chip revision */
uint chippkg; /* chip package option */
- u32 chipst; /* chip status */
};
struct pci_dev;
void __iomem *curmap; /* current regs va */
void __iomem *regs[SI_MAXCORES]; /* other regs va */
+ u32 chipst; /* chip status */
uint curidx; /* current core index */
+ uint buscoreidx; /* buscore index */
uint numcores; /* # discovered cores */
uint coreid[SI_MAXCORES]; /* id of each core */
u32 coresba[SI_MAXCORES]; /* backplane address of each core */