When setting the clock source for one of the 'A' encoders to operate in
"counter" mode in `s626_set_mode_a()`, bitshift the clock source value by
`S626_CRABIT_CLKSRC_A` for consistency with the other modes. This has
no effect on the value since `S626_CRABIT_CLKSRC_A` is 0.
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
break;
default: /* Counter Mode: */
/* Select ENC_C and ENC_D as clock/direction inputs. */
- cra |= S626_CLKSRC_COUNTER;
+ cra |= S626_CLKSRC_COUNTER << S626_CRABIT_CLKSRC_A;
/* Clock polarity is passed through. */
cra |= (setup & S626_STDMSK_CLKPOL) <<
(S626_CRABIT_CLKPOL_A - S626_STDBIT_CLKPOL);