clk: cygnus: Convert all macros to all caps

The macros that are being used to initialize the values of the clk
structures should be all caps.  Find and replace all of them with their
relevant counterparts.

Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
index 316c603376619266378e42fc88b0ab2540defbb0..aac82c671eeb74e14e072562c12d95b47433bd47 100644 (file)
--- a/drivers/clk/bcm/clk-cygnus.c
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -23,28 +23,28 @@
 #include <dt-bindings/clock/bcm-cygnus.h>
 #include "clk-iproc.h"
 
-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
 
-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
        .pwr_shift = ps, .iso_shift = is }
 
-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
 
-#define asiu_div_val(o, es, hs, hw, ls, lw) \
+#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
                { .offset = o, .en_shift = es, .high_shift = hs, \
                .high_width = hw, .low_shift = ls, .low_width = lw }
 
-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
        .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
        .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
        .ka_width = kaw }
 
-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
 
-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
        .hold_shift = hs, .bypass_shift = bs }
 
-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
+#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
 
 static void __init cygnus_armpll_init(struct device_node *node)
 {
@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
 static const struct iproc_pll_ctrl genpll = {
        .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
                IPROC_CLK_PLL_NEEDS_SW_CFG,
-       .aon = aon_val(0x0, 2, 1, 0),
-       .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
-       .sw_ctrl = sw_ctrl_val(0x10, 31),
-       .ndiv_int = reg_val(0x10, 20, 10),
-       .ndiv_frac = reg_val(0x10, 0, 20),
-       .pdiv = reg_val(0x14, 0, 4),
-       .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
-       .status = reg_val(0x28, 12, 1),
+       .aon = AON_VAL(0x0, 2, 1, 0),
+       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
+       .sw_ctrl = SW_CTRL_VAL(0x10, 31),
+       .ndiv_int = REG_VAL(0x10, 20, 10),
+       .ndiv_frac = REG_VAL(0x10, 0, 20),
+       .pdiv = REG_VAL(0x14, 0, 4),
+       .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
+       .status = REG_VAL(0x28, 12, 1),
 };
 
 static const struct iproc_clk_ctrl genpll_clk[] = {
        [BCM_CYGNUS_GENPLL_AXI21_CLK] = {
                .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x4, 6, 0, 12),
-               .mdiv = reg_val(0x20, 0, 8),
+               .enable = ENABLE_VAL(0x4, 6, 0, 12),
+               .mdiv = REG_VAL(0x20, 0, 8),
        },
        [BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
                .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x4, 7, 1, 13),
-               .mdiv = reg_val(0x20, 10, 8),
+               .enable = ENABLE_VAL(0x4, 7, 1, 13),
+               .mdiv = REG_VAL(0x20, 10, 8),
        },
        [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
                .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x4, 8, 2, 14),
-               .mdiv = reg_val(0x20, 20, 8),
+               .enable = ENABLE_VAL(0x4, 8, 2, 14),
+               .mdiv = REG_VAL(0x20, 20, 8),
        },
        [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
                .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x4, 9, 3, 15),
-               .mdiv = reg_val(0x24, 0, 8),
+               .enable = ENABLE_VAL(0x4, 9, 3, 15),
+               .mdiv = REG_VAL(0x24, 0, 8),
        },
        [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
                .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x4, 10, 4, 16),
-               .mdiv = reg_val(0x24, 10, 8),
+               .enable = ENABLE_VAL(0x4, 10, 4, 16),
+               .mdiv = REG_VAL(0x24, 10, 8),
        },
        [BCM_CYGNUS_GENPLL_CAN_CLK] = {
                .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x4, 11, 5, 17),
-               .mdiv = reg_val(0x24, 20, 8),
+               .enable = ENABLE_VAL(0x4, 11, 5, 17),
+               .mdiv = REG_VAL(0x24, 20, 8),
        },
 };
 
@@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
 
 static const struct iproc_pll_ctrl lcpll0 = {
        .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
-       .aon = aon_val(0x0, 2, 5, 4),
-       .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
-       .sw_ctrl = sw_ctrl_val(0x4, 31),
-       .ndiv_int = reg_val(0x4, 16, 10),
-       .pdiv = reg_val(0x4, 26, 4),
-       .vco_ctrl = vco_ctrl_val(0x10, 0x14),
-       .status = reg_val(0x18, 12, 1),
+       .aon = AON_VAL(0x0, 2, 5, 4),
+       .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
+       .sw_ctrl = SW_CTRL_VAL(0x4, 31),
+       .ndiv_int = REG_VAL(0x4, 16, 10),
+       .pdiv = REG_VAL(0x4, 26, 4),
+       .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
+       .status = REG_VAL(0x18, 12, 1),
 };
 
 static const struct iproc_clk_ctrl lcpll0_clk[] = {
        [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
                .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x0, 7, 1, 13),
-               .mdiv = reg_val(0x8, 0, 8),
+               .enable = ENABLE_VAL(0x0, 7, 1, 13),
+               .mdiv = REG_VAL(0x8, 0, 8),
        },
        [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
                .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x0, 8, 2, 14),
-               .mdiv = reg_val(0x8, 10, 8),
+               .enable = ENABLE_VAL(0x0, 8, 2, 14),
+               .mdiv = REG_VAL(0x8, 10, 8),
        },
        [BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
                .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x0, 9, 3, 15),
-               .mdiv = reg_val(0x8, 20, 8),
+               .enable = ENABLE_VAL(0x0, 9, 3, 15),
+               .mdiv = REG_VAL(0x8, 20, 8),
        },
        [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
                .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x0, 10, 4, 16),
-               .mdiv = reg_val(0xc, 0, 8),
+               .enable = ENABLE_VAL(0x0, 10, 4, 16),
+               .mdiv = REG_VAL(0xc, 0, 8),
        },
        [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
                .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x0, 11, 5, 17),
-               .mdiv = reg_val(0xc, 10, 8),
+               .enable = ENABLE_VAL(0x0, 11, 5, 17),
+               .mdiv = REG_VAL(0xc, 10, 8),
        },
        [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
                .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
                .flags = IPROC_CLK_AON,
-               .enable = enable_val(0x0, 12, 6, 18),
-               .mdiv = reg_val(0xc, 20, 8),
+               .enable = ENABLE_VAL(0x0, 12, 6, 18),
+               .mdiv = REG_VAL(0xc, 20, 8),
        },
 };
 
@@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param mipipll_vco_params[] = {
 static const struct iproc_pll_ctrl mipipll = {
        .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
                 IPROC_CLK_NEEDS_READ_BACK,
-       .aon = aon_val(0x0, 4, 17, 16),
-       .asiu = asiu_gate_val(0x0, 3),
-       .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
-       .ndiv_int = reg_val(0x10, 20, 10),
-       .ndiv_frac = reg_val(0x10, 0, 20),
-       .pdiv = reg_val(0x14, 0, 4),
-       .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
-       .status = reg_val(0x28, 12, 1),
+       .aon = AON_VAL(0x0, 4, 17, 16),
+       .asiu = ASIU_GATE_VAL(0x0, 3),
+       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
+       .ndiv_int = REG_VAL(0x10, 20, 10),
+       .ndiv_frac = REG_VAL(0x10, 0, 20),
+       .pdiv = REG_VAL(0x14, 0, 4),
+       .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
+       .status = REG_VAL(0x28, 12, 1),
 };
 
 static const struct iproc_clk_ctrl mipipll_clk[] = {
        [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
                .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
                .flags = IPROC_CLK_NEEDS_READ_BACK,
-               .enable = enable_val(0x4, 12, 6, 18),
-               .mdiv = reg_val(0x20, 0, 8),
+               .enable = ENABLE_VAL(0x4, 12, 6, 18),
+               .mdiv = REG_VAL(0x20, 0, 8),
        },
        [BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
                .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
                .flags = IPROC_CLK_NEEDS_READ_BACK,
-               .enable = enable_val(0x4, 13, 7, 19),
-               .mdiv = reg_val(0x20, 10, 8),
+               .enable = ENABLE_VAL(0x4, 13, 7, 19),
+               .mdiv = REG_VAL(0x20, 10, 8),
        },
        [BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
                .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
                .flags = IPROC_CLK_NEEDS_READ_BACK,
-               .enable = enable_val(0x4, 14, 8, 20),
-               .mdiv = reg_val(0x20, 20, 8),
+               .enable = ENABLE_VAL(0x4, 14, 8, 20),
+               .mdiv = REG_VAL(0x20, 20, 8),
        },
        [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
                .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
                .flags = IPROC_CLK_NEEDS_READ_BACK,
-               .enable = enable_val(0x4, 15, 9, 21),
-               .mdiv = reg_val(0x24, 0, 8),
+               .enable = ENABLE_VAL(0x4, 15, 9, 21),
+               .mdiv = REG_VAL(0x24, 0, 8),
        },
        [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
                .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
                .flags = IPROC_CLK_NEEDS_READ_BACK,
-               .enable = enable_val(0x4, 16, 10, 22),
-               .mdiv = reg_val(0x24, 10, 8),
+               .enable = ENABLE_VAL(0x4, 16, 10, 22),
+               .mdiv = REG_VAL(0x24, 10, 8),
        },
        [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
                .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
                .flags = IPROC_CLK_NEEDS_READ_BACK,
-               .enable = enable_val(0x4, 17, 11, 23),
-               .mdiv = reg_val(0x24, 20, 8),
+               .enable = ENABLE_VAL(0x4, 17, 11, 23),
+               .mdiv = REG_VAL(0x24, 20, 8),
        },
 };
 
@@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_init(struct device_node *node)
 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
 
 static const struct iproc_asiu_div asiu_div[] = {
-       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10),
-       [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10),
-       [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10),
+       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10),
+       [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10),
+       [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),
 };
 
 static const struct iproc_asiu_gate asiu_gate[] = {
-       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7),
-       [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9),
-       [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0),
+       [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7),
+       [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9),
+       [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
 };
 
 static void __init cygnus_asiu_init(struct device_node *node)