clk: mediatek: add 13mhz clock for MT8173

Add 13mhz clock used by GPT timer in infracfg.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 90eff85f4285ec10415509ba8013b63d623f94cb..9ea6aa1f30d52dd7b0f4ef7bf63477749618d5c0 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -619,6 +619,10 @@ static const struct mtk_gate infra_clks[] __initconst = {
        GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
 };
 
+static const struct mtk_fixed_factor infra_divs[] __initconst = {
+       FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
+};
+
 static const struct mtk_gate_regs peri0_cg_regs = {
        .set_ofs = 0x0008,
        .clr_ofs = 0x0010,
@@ -754,6 +758,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
 
        mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
                                                clk_data);
+       mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
 
        r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
        if (r)

diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 4ad76ed882ad3abd9c61dc730a66a9c6753262a1..fa2a2bb09d154456e7fd841327a3bafcb8e76945 100644 (file)
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -187,7 +187,8 @@
 #define CLK_INFRA_CEC                  9
 #define CLK_INFRA_PMICSPI              10
 #define CLK_INFRA_PMICWRAP             11
-#define CLK_INFRA_NR_CLK               12
+#define CLK_INFRA_CLK_13M              12
+#define CLK_INFRA_NR_CLK               13
 
 /* PERI_SYS */