[POWERPC] spufs: fix class0 interrupt assignment

The class zero interrupt handling for spus was confusing alignment and
error interrupts, so swap them.

Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index db82f503ba2cc53ad11cfca0ac2193a9ff8d2a99..b306723abb87ba2f07f3169cfed713e54dc9e152 100644 (file)
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -168,12 +168,12 @@ spu_irq_class_0_bottom(struct spu *spu)
 
        stat &= mask;
 
-       if (stat & 1) /* invalid MFC DMA */
-               __spu_trap_invalid_dma(spu);
-
-       if (stat & 2) /* invalid DMA alignment */
+       if (stat & 1) /* invalid DMA alignment */
                __spu_trap_dma_align(spu);
 
+       if (stat & 2) /* invalid MFC DMA */
+               __spu_trap_invalid_dma(spu);
+
        if (stat & 4) /* error on SPU */
                __spu_trap_error(spu);