net: dsa: mv88e6xxx: prefix Port Egress Rate Control macros

For implicit namespacing and clarity, prefix the common Port Egress Rate
Control and Port Egress Rate Control 2 registers macros with
MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2.

Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index efc57003b9eefbf9034f265d2606c183210eebf3..8146c94e394d21d985bf1fb823cd39a200176cb6 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1897,7 +1897,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
                return err;
 
        /* Egress rate control 2: disable egress rate control. */
-       err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
+       err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+                                  0x0000);
        if (err)
                return err;
 

diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index ad86b2e30ac538c240f6462c30b9730d6db1b3d5..595f842c955be01e56045040eff1eebc8675b28e 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -859,12 +859,14 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
 
 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
 {
-       return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000);
+       return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
+                                   0x0000);
 }
 
 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
 {
-       return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001);
+       return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
+                                   0x0001);
 }
 
 /* Offset 0x0C: Port ATU Control */

diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index ce236f06db6d5c7d8297c10e200908af53d726a6..5bcba657a111ea570404b6190d54850faaa07297 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -177,8 +177,12 @@
 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR            0x0010
 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK              0x000f
 
-#define PORT_RATE_CONTROL      0x09
-#define PORT_RATE_CONTROL_2    0x0a
+/* Offset 0x09: Egress Rate Control */
+#define MV88E6XXX_PORT_EGRESS_RATE_CTL1                0x09
+
+/* Offset 0x0A: Egress Rate Control 2 */
+#define MV88E6XXX_PORT_EGRESS_RATE_CTL2                0x0a
+
 #define PORT_ASSOC_VECTOR      0x0b
 #define PORT_ASSOC_VECTOR_HOLD_AT_1            BIT(15)
 #define PORT_ASSOC_VECTOR_INT_AGE_OUT          BIT(14)