ARM: l2c: zynq: remove cache size override

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 6fcc584c1a110fb1986ee9ddbb0ae99bfbf907a4..1e617a6dedc3435979747c302509ee657ac5976e 100644 (file)
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -70,7 +70,7 @@ static void __init zynq_init_machine(void)
        /*
         * 64KB way size, 8-way associativity, parity disabled
         */
-       l2x0_of_init(0x02060000, 0xF0F0FFFF);
+       l2x0_of_init(0x02000000, 0xf0ffffff);
 
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);