e1000: reorder pci-e infor struct
authorJeff Kirsher <jeffrey.t.kirsher@intel.com>
Wed, 1 Nov 2006 16:47:47 +0000 (08:47 -0800)
committerJeff Garzik <jeff@garzik.org>
Sat, 2 Dec 2006 05:11:59 +0000 (00:11 -0500)
Order pci-e capability struct according to bus/pci bus width ordering
preserving the hard pci spec numbers.

Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/e1000/e1000_hw.h

index 31bea32158417cfcee03f93269294e57f8970b31..f247f264a57b7b83e255a44647d0844f2997d238 100644 (file)
@@ -128,11 +128,13 @@ typedef enum {
 /* PCI bus widths */
 typedef enum {
     e1000_bus_width_unknown = 0,
+    /* These PCIe values should literally match the possible return values
+     * from config space */
+    e1000_bus_width_pciex_1 = 1,
+    e1000_bus_width_pciex_2 = 2,
+    e1000_bus_width_pciex_4 = 4,
     e1000_bus_width_32,
     e1000_bus_width_64,
-    e1000_bus_width_pciex_1,
-    e1000_bus_width_pciex_2,
-    e1000_bus_width_pciex_4,
     e1000_bus_width_reserved
 } e1000_bus_width;