drm/i915: fix Haswell pfit power well check v2

We can't read the pfit regs if the power well is off, so use the cached
value.

v2: re-add lost comment (Jesse)
    make sure the crtc using the fitter is actually enabled (Jesse)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Drop now unused dev_priv, as spotted by Mika.]
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 650433790813883858e7ca8ad8d946dc7cbbae65..de8be7595a6291e347645c8cdedd3d2b05210d0c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5906,7 +5906,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 
 static void haswell_modeset_global_resources(struct drm_device *dev)
 {
-       struct drm_i915_private *dev_priv = dev->dev_private;
        bool enable = false;
        struct intel_crtc *crtc;
        struct intel_encoder *encoder;
@@ -5918,7 +5917,7 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
                 * sequence that's not yet available. Just in case desktop eDP
                 * on PORT D is possible on haswell, too. */
                /* Even the eDP panel fitter is outside the always-on well. */
-               if (I915_READ(PF_WIN_SZ(crtc->pipe)))
+               if (crtc->config.pch_pfit.size && crtc->base.enabled)
                        enable = true;
        }