void mali_l2_cache_reset(struct mali_l2_cache_core *cache)
{
+ if (cache && cache->pm_domain && cache->pm_domain->state == MALI_PM_DOMAIN_OFF) {
+ return;
+ }
+
/* Invalidate cache (just to keep it in a known state at startup) */
mali_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_COMMAND, MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
#include <asm/io.h>
#include "mali_clock.h"
-unsigned int mali_default_clock_step = MALI_CLOCK_318;
+unsigned int mali_default_clock_step = MALI_CLOCK_318;// MALI_CLOCK_318;
static DEFINE_SPINLOCK(lock);
clrbits_le32(P_HHI_MALI_CLK_CNTL, (0x7F | (0x7 << 9)));
writel(clock, P_HHI_MALI_CLK_CNTL | (1 << 8)); /* set clock to 333MHZ.*/
setbits_le32(P_HHI_MALI_CLK_CNTL, 1 << 8);
- writel(0x0001c007, P_HHI_MPLL_CNTL4);
}
void disable_clock(void)
spin_unlock_irqrestore(&lock, flags);
}
+u32 mali_clock_test(void)
+{
+ unsigned int clk_mux = 35;
+ unsigned int regval = 0;
+ /// Set the measurement gate to 64uS
+ clrsetbits_le32(P_MSR_CLK_REG0,0xffff,121);///122us
+
+ // Disable continuous measurement
+ // disable interrupts
+ clrsetbits_le32(P_MSR_CLK_REG0,
+ ((1 << 18) | (1 << 17)|(0x1f << 20)),///clrbits
+ (clk_mux << 20) | /// Select MUX
+ (1 << 19) | /// enable the clock
+ (1 << 16));
+ // Wait for the measurement to be done
+ regval = readl(P_MSR_CLK_REG0);
+ do {
+ regval = readl(P_MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ // disable measuring
+ clrbits_le32(P_MSR_CLK_REG0, (1 << 16));
+ regval = (readl(P_MSR_CLK_REG2)) & 0x000FFFFF;
+ regval += (regval/10000) * 6;
+ // Return value in MHz*measured_val
+ return (regval << 13);
+}
+
+
void enable_clock(void)
{
unsigned long flags;
{ 0 , (43 * 256) / 100.0 + 0.5},
{ (40 * 256) / 100.0 + 0.5, (53 * 256) / 100.0 + 0.5},
{ (50 * 256) / 100.0 + 0.5, (92 * 256) / 100.0 + 0.5},
- { (87 * 256) / 100.0 + 0.5, 256 }
+ { (89 * 256) / 100.0 + 0.5, 256 }
};
enum mali_pp_scale_threshold_t {
MALI_DEBUG_PRINT(3, (" %d \n", currentStep));
u32 utilization = data->utilization_gpu;
- if (utilization > mali_dvfs_threshold[currentStep].upthreshold) {
+ if (utilization >= mali_dvfs_threshold[currentStep].upthreshold) {
+ //printk(" > utilization:%d currentStep:%d. upthreshold:%d.\n", utilization, currentStep, mali_dvfs_threshold[currentStep].upthreshold );
if (utilization < mali_utilization_high && currentStep < max_mali_clock)
currentStep ++;
else
} else {
enable_one_core();
}
+ schedule_work(&wq_work);
} else if (utilization < mali_dvfs_threshold[currentStep].downthreshold && currentStep > min_mali_clock) {
+ //printk(" < utilization:%d currentStep:%d. downthreshold:%d.\n", utilization, currentStep,mali_dvfs_threshold[currentStep].downthreshold );
currentStep--;
MALI_DEBUG_PRINT(2, ("Mali clock set %d..\n",currentStep));
+ schedule_work(&wq_work);
} else {
- if (data->utilization_pp < mali_pp_scale_threshold[MALI_PP_THRESHOLD_40])
+ //printk(" else utilization:%d currentStep:%d. downthreshold:%d.\n", utilization, currentStep,mali_dvfs_threshold[currentStep].downthreshold );
+ if (data->utilization_pp < mali_pp_scale_threshold[MALI_PP_THRESHOLD_30])
disable_one_core();
return;
}
u32 get_max_pp_num(void)
{
- printk(" %d->%s \n", __LINE__, __FUNCTION__);
return num_cores_total;
}
u32 set_max_pp_num(u32 num)
{
- printk(" %d->%s \n", __LINE__, __FUNCTION__);
if (num > MALI_PP_NUMBER || num < min_pp_num )
return -1;
num_cores_total = num;
};
static int scaling_mode = MALI_PP_FS_SCALING;
-module_param(scaling_mode, int, 0664);
-MODULE_PARM_DESC(scaling_mode, "0 disable, 1 pp, 2 fs, 4 double");
+//module_param(scaling_mode, int, 0664);
+//MODULE_PARM_DESC(scaling_mode, "0 disable, 1 pp, 2 fs, 4 double");
static int last_scaling_mode;
static void mali_platform_device_release(struct device *device);
void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data)
{
+ #if 0
if (last_scaling_mode != scaling_mode) {
reset_mali_scaling_stat();
last_scaling_mode = scaling_mode;
}
+ #endif
switch (scaling_mode) {
case MALI_PP_FS_SCALING:
mali_pp_fs_scaling_update(data);