Some Arizona chips have a higher frequency for the FLL VCO, support this
in the common code.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
/* Apply the division for our remaining calculations */
Fref /= div;
- /* Fvco should be 90-100MHz; don't check the upper bound */
+ /* Fvco should be over the targt; don't check the upper bound */
div = 1;
- while (Fout * div < 90000000) {
+ while (Fout * div < 90000000 * fll->vco_mult) {
div++;
if (div > 7) {
arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
return -EINVAL;
}
}
- target = Fout * div;
+ target = Fout * div / fll->vco_mult;
cfg->outdiv = div;
arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
struct arizona *arizona;
int id;
unsigned int base;
+ unsigned int vco_mult;
struct completion lock;
struct completion ok;
wm5102->core.arizona = arizona;
+ for (i = 0; i < ARRAY_SIZE(wm5102->fll); i++)
+ wm5102->fll[i].vco_mult = 1;
+
arizona_init_fll(arizona, 1, ARIZONA_FLL1_CONTROL_1 - 1,
ARIZONA_IRQ_FLL1_LOCK, ARIZONA_IRQ_FLL1_CLOCK_OK,
&wm5102->fll[0]);