Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k"

As I found by chance while merging another patch, the usage of
a dma-mask in this DT node is wrong for multiple reasons:

- dma-masks are a Linux specific concept, not a general
  hardware feature
- In DT, we use the "dma-ranges" property to describe how DMA
  addresses related between devices.
- The 40-bit mask appears to be completely unnecessary here, as
  the SoC cannot address that much memory anyway, so simply
  asking for a 64-bit mask (as supported by the device) should
  succeed anyway.

The patch to remove the parsing of the property is getting merged
through the crypto tree.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index f611e843094c6d2e7decb3ce3e8f92384e921165..726528ce54e9650fe2b0ebfc085b0f0753e876d8 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -270,7 +270,6 @@
                                interrupt-names = "mem", "ring0", "ring1",
                                "ring2", "ring3", "eip";
                                clocks = <&cpm_clk 1 26>;
-                               dma-mask = <0xff 0xffffffff>;
                        };
                };
 

diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 84d3bd80eb51861f04a5aa9257edef50a9f9c0f6..95f8e5f607f608d2ec1bd258e1eec76f0d4b8528 100644 (file)
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -261,7 +261,6 @@
                                interrupt-names = "mem", "ring0", "ring1",
                                                  "ring2", "ring3", "eip";
                                clocks = <&cps_clk 1 26>;
-                               dma-mask = <0xff 0xffffffff>;
                                /*
                                 * The cryptographic engine found on the cp110
                                 * master is enabled by default at the SoC