clk: rockchip: fix clk_i2sout parent selection bits on rk3399

commit a64ad008980c65d38e6cf6858429c78e6b740c41 upstream.

Register, shift and mask were wrong according to datasheet.

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 6847120b61cdeff87b7de7995c412df5a7d6449c..62d0a69f8da0129b0c226ffda2e61bf6547de386 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -630,7 +630,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
        MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
                        RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
        COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
-                       RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
+                       RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
                        RK3399_CLKGATE_CON(8), 12, GFLAGS),
 
        /* uart */