mlxsw: pci: Add KVD size relate resources

Add KVD size, and minimum sizes for the single and double
sections resources to resources query.

Signed-off-by: Nogah Frankel <nogahf@mellanox.com>
Reviewed-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h
index 558d1ce895315c4575c3d9abf53c3d3c25f128ba..76ad566a0421fa4239146a47884879d291cb46f1 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/core.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/core.h
@@ -267,10 +267,16 @@ struct mlxsw_driver {
 struct mlxsw_resources {
        u8      max_span_valid:1,
                max_lag_valid:1,
-               max_ports_in_lag_valid:1;
+               max_ports_in_lag_valid:1,
+               kvd_size_valid:1,
+               kvd_single_min_size_valid:1,
+               kvd_double_min_size_valid:1;
        u8      max_span;
        u8      max_lag;
        u8      max_ports_in_lag;
+       u32     kvd_size;
+       u32     kvd_single_min_size;
+       u32     kvd_double_min_size;
 };
 
 struct mlxsw_resources *mlxsw_core_resources_get(struct mlxsw_core *mlxsw_core);

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index 57c2d3474bb6f4f11cb52a9bb60cedaecf307834..7b2ab1ec1290334a12098b0e0c3181cf7f6b6df1 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -1158,6 +1158,9 @@ mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci,
 #define MLXSW_MAX_SPAN_ID 0x2420
 #define MLXSW_MAX_LAG_ID 0x2520
 #define MLXSW_MAX_PORTS_IN_LAG_ID 0x2521
+#define MLXSW_KVD_SIZE_ID 0x1001
+#define MLXSW_KVD_SINGLE_MIN_SIZE_ID 0x1002
+#define MLXSW_KVD_DOUBLE_MIN_SIZE_ID 0x1003
 #define MLXSW_RESOURCES_QUERY_MAX_QUERIES 100
 #define MLXSW_RESOURCES_PER_QUERY 32
 
@@ -1177,6 +1180,18 @@ static void mlxsw_pci_resources_query_parse(int id, u64 val,
                resources->max_ports_in_lag = val;
                resources->max_ports_in_lag_valid = 1;
                break;
+       case MLXSW_KVD_SIZE_ID:
+               resources->kvd_size = val;
+               resources->kvd_size_valid = 1;
+               break;
+       case MLXSW_KVD_SINGLE_MIN_SIZE_ID:
+               resources->kvd_single_min_size = val;
+               resources->kvd_single_min_size_valid = 1;
+               break;
+       case MLXSW_KVD_DOUBLE_MIN_SIZE_ID:
+               resources->kvd_double_min_size = val;
+               resources->kvd_double_min_size_valid = 1;
+               break;
        default:
                break;
        }