net/faraday: Adapt for Aspeed SoCs

The RXDES and TXDES registers bits in the ftgmac100 indicates EDO{R,T}R
at bit position 15 for the Faraday Tech IP. However, the version of this
IP present in the Aspeed SoCs has these bits at position 30 in the
registers.

It appers that ast2400 SoCs support both positions, with the 15th bit
marked as reserved but still functional. In the ast2500 this bit is
reused for another function, so we need a work around.

This was confirmed with engineers from Aspeed that using bit 30 is
correct for both the ast2400 and ast2500 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c
index 62a88d1a1f996ea70b2774ec9c5e77578eb9d4d6..47f512224b573c8367feb40388f583f015ca0f40 100644 (file)
--- a/drivers/net/ethernet/faraday/ftgmac100.c
+++ b/drivers/net/ethernet/faraday/ftgmac100.c
@@ -1345,9 +1345,6 @@ static int ftgmac100_probe(struct platform_device *pdev)
        priv->netdev = netdev;
        priv->dev = &pdev->dev;
 
-       priv->rxdes0_edorr_mask = BIT(15);
-       priv->txdes0_edotr_mask = BIT(15);
-
        spin_lock_init(&priv->tx_lock);
 
        /* initialize NAPI */
@@ -1381,6 +1378,16 @@ static int ftgmac100_probe(struct platform_device *pdev)
                              FTGMAC100_INT_PHYSTS_CHG |
                              FTGMAC100_INT_RPKT_BUF |
                              FTGMAC100_INT_NO_RXBUF);
+
+       if (of_machine_is_compatible("aspeed,ast2400") ||
+           of_machine_is_compatible("aspeed,ast2500")) {
+               priv->rxdes0_edorr_mask = BIT(30);
+               priv->txdes0_edotr_mask = BIT(30);
+       } else {
+               priv->rxdes0_edorr_mask = BIT(15);
+               priv->txdes0_edotr_mask = BIT(15);
+       }
+
        if (pdev->dev.of_node &&
            of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
                if (!IS_ENABLED(CONFIG_NET_NCSI)) {