drm/radeon: allocate PPLLs from low to high
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 5 Oct 2012 14:22:02 +0000 (10:22 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 15 Oct 2012 17:21:00 +0000 (13:21 -0400)
The order shouldn't matter, but there have been problems
reported on certain older asics.  This behaves more
like the original code before the PPLL allocation
rework.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Markus Trippelsdorf <markus@trippelsdorf.de>
drivers/gpu/drm/radeon/atombios_crtc.c

index 96184d02c8d924969527c307d137a55664c6f96c..2e566e123e9e747e988f7482a3a5b827b7ca121f 100644 (file)
@@ -1690,10 +1690,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
                }
                /* all other cases */
                pll_in_use = radeon_get_pll_use_mask(crtc);
-               if (!(pll_in_use & (1 << ATOM_PPLL2)))
-                       return ATOM_PPLL2;
                if (!(pll_in_use & (1 << ATOM_PPLL1)))
                        return ATOM_PPLL1;
+               if (!(pll_in_use & (1 << ATOM_PPLL2)))
+                       return ATOM_PPLL2;
                DRM_ERROR("unable to allocate a PPLL\n");
                return ATOM_PPLL_INVALID;
        } else {
@@ -1715,10 +1715,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
                        }
                        /* all other cases */
                        pll_in_use = radeon_get_pll_use_mask(crtc);
-                       if (!(pll_in_use & (1 << ATOM_PPLL2)))
-                               return ATOM_PPLL2;
                        if (!(pll_in_use & (1 << ATOM_PPLL1)))
                                return ATOM_PPLL1;
+                       if (!(pll_in_use & (1 << ATOM_PPLL2)))
+                               return ATOM_PPLL2;
                        DRM_ERROR("unable to allocate a PPLL\n");
                        return ATOM_PPLL_INVALID;
                } else {