ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 50f259b20f94bec2bacedf8d5bb1a39220f00144..00b50db57c9c0f7ab4111bbdba06d3fd0bdc93ad 100644 (file)
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -129,6 +129,7 @@
                                compatible = "marvell,aurora-outer-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
+                               cache-level = <2>;
                                cache-unified;
                                wt-override;
                        };

diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 448af3352175db1e8d91d49f3242f40880faed90..013d63f69e361e60bbe96466bec1883388155889 100644 (file)
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -79,6 +79,7 @@
                                compatible = "marvell,aurora-system-cache";
                                reg = <0x08000 0x1000>;
                                cache-id-part = <0x100>;
+                               cache-level = <2>;
                                cache-unified;
                                wt-override;
                        };