drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-only

This register is read-only, so we have never actually set
OCL2_LDOFUSE_PWR_DIS in it as specified by the specification. Add a code
comment about this. I filed a specification update request to clarify
this there.

CC: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: David Weinehall <david.weinehall@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-4-git-send-email-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 921edf183d226f9b2606be88f8367542347052e0..2b9e79d59c1387c84d73932b808bdb9068fe15e3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1798,6 +1798,9 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
         * enabled.
         * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
         * power down the second channel on PHY0 as well.
+        *
+        * FIXME: Clarify programming of the following, the register is
+        * read-only with bit 6 fixed at 0 at least in stepping A.
         */
        if (phy == DPIO_PHY1)
                val |= OCL2_LDOFUSE_PWR_DIS;