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ARM: dts: fix L2 address in Hi3620
authorHaojian Zhuang <haojian.zhuang@linaro.org>
Wed, 2 Apr 2014 13:31:50 +0000 (21:31 +0800)
committerArnd Bergmann <arnd@arndb.de>
Sat, 26 Jul 2014 10:14:32 +0000 (12:14 +0200)
Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm/boot/dts/hi3620.dtsi patch | blob | blame | history

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index ab1116d086be82bc405f599cd3f2677a749fae42..83a5b8685bd961818bfa8c9d6bea6bc3bff4ff24 100644 (file)
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -73,7 +73,7 @@
 
                L2: l2-cache {
                        compatible = "arm,pl310-cache";
-                       reg = <0xfc10000 0x100000>;
+                       reg = <0x100000 0x100000>;
                        interrupts = <0 15 4>;
                        cache-unified;
                        cache-level = <2>;