#define OSC_CLK (0xa04068)
#define OSC_CLK_FORCE_CONTROL (0x8)
-/* SECURE boot registers */
-#define LMPM_SECURE_BOOT_CONFIG_ADDR (0x100)
-enum secure_boot_config_reg {
- LMPM_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
- LMPM_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
-};
-
-#define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0 (0xA01E30)
-#define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR (0x1E30)
-#define LMPM_SECURE_BOOT_CPU2_STATUS_ADDR (0x1E34)
-enum secure_boot_status_reg {
- LMPM_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000001,
- LMPM_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
- LMPM_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
- LMPM_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
- LMPM_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
- LMPM_SECURE_BOOT_STATUS_SUCCESS = 0x00000003,
-};
-
#define FH_UCODE_LOAD_STATUS (0x1AF0)
#define CSR_UCODE_LOAD_STATUS_ADDR (0x1E70)
enum secure_load_status_reg {
#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
-#define LMPM_SECURE_TIME_OUT (100) /* 10 micro */
-
/* Rx FIFO */
#define RXF_SIZE_ADDR (0xa00c88)
#define RXF_RD_D_SPACE (0xa00c40)
{
int ret = 0;
int first_ucode_section;
- u32 reg;
IWL_DEBUG_FW(trans, "working with %s CPU\n",
image->is_dual_cpus ? "Dual" : "Single");
if (ret)
return ret;
- /* wait for image verification to complete */
- ret = iwl_poll_prph_bit(trans, LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0,
- LMPM_SECURE_BOOT_STATUS_SUCCESS,
- LMPM_SECURE_BOOT_STATUS_SUCCESS,
- LMPM_SECURE_TIME_OUT);
- if (ret < 0) {
- reg = iwl_read_prph(trans,
- LMPM_SECURE_BOOT_CPU1_STATUS_ADDR_B0);
-
- IWL_ERR(trans, "Timeout on secure boot process, reg = %x\n",
- reg);
- return ret;
- }
-
return 0;
}