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drm: G33-class hardware has a newer 965-style MCH (no DCC register).
authorEric Anholt <eric@anholt.net>
Mon, 15 Sep 2008 20:13:34 +0000 (13:13 -0700)
committerDave Airlie <airlied@linux.ie>
Fri, 17 Oct 2008 21:10:52 +0000 (07:10 +1000)
Fixes bad software fallback rendering in Mesa in dual-channel configurations.

d9a2470012588dc5313a5ac8bb2f03575af00e99

Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/i915/i915_gem_tiling.c patch | blob | blame | history

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 0c1b3a0834e100b8227ad010c54bcf6d4e62480d..6b3f1e4a34a1939a42e67f3298d47d8fb26c66cc 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                 */
                swizzle_x = I915_BIT_6_SWIZZLE_NONE;
                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-       } else if (!IS_I965G(dev) || IS_I965GM(dev)) {
+       } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
                uint32_t dcc;
 
                /* On 915-945 and GM965, channel interleave by the CPU is