clk: tegra: Mark timer clock as critical

The timer clock feeds the timer block, which, among other things, is
used to drive the SOR lane sequencer. Since the Tegra timer driver is
not enabled on 64-bit ARM, nothing currently claims that clock and it
gets disabled by the common clock framework at late_init time.

Given the non-obvious dependencies, the timer clock can be considered
a critical part of the SoC infrastructure, requiring its clock source
to be always on.

Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index af85c8aeaf5a0b4d77ffa1f0c7b412755dbbb2d6..4ce4e7fb1124d0aa38323454af5a782edffae42c 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -792,7 +792,7 @@ static struct tegra_periph_init_data periph_clks[] = {
 
 static struct tegra_periph_init_data gate_clks[] = {
        GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
-       GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
+       GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
        GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
        GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
        GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),