x86/pci: Enable pci root res read out for 32bit too

Should be good for 32bit too.

-v3: cast res->start
-v4: according to Linus, to use %pR instead of cast

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
LKML-Reference: <1265793639-15071-9-git-send-email-yinghai@kernel.org>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index 39fba37f702f40b61eb8d5c61b8716a3b59ee5bb..0b7d3e9593e157cb328db23c922f5c3c6cde8d20 100644 (file)
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -14,8 +14,7 @@ obj-$(CONFIG_X86_VISWS)               += visws.o
 obj-$(CONFIG_X86_NUMAQ)                += numaq_32.o
 
 obj-y                          += common.o early.o
-obj-y                          += amd_bus.o
-obj-$(CONFIG_X86_64)           += bus_numa.o
+obj-y                          += amd_bus.o bus_numa.o
 
 ifeq ($(CONFIG_PCI_DEBUG),y)
 EXTRA_CFLAGS += -DDEBUG

diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index f7e13b63154e6055696f8b4723af27c63e16bf2f..ea6072fcf3d4b86cd959d816551ddde3622090dc 100644 (file)
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -6,9 +6,7 @@
 
 #include <asm/pci_x86.h>
 
-#ifdef CONFIG_X86_64
 #include <asm/pci-direct.h>
-#endif
 
 #include "bus_numa.h"
 
@@ -17,8 +15,6 @@
  * also get peer root bus resource for io,mmio
  */
 
-#ifdef CONFIG_X86_64
-
 struct pci_hostbridge_probe {
        u32 bus;
        u32 slot;
@@ -339,24 +335,14 @@ static int __init early_fill_mp_bus_info(void)
                       info->bus_min, info->bus_max, info->node, info->link);
                for (j = 0; j < res_num; j++) {
                        res = &info->res[j];
-                       printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
-                              busnum, j,
-                              (res->flags & IORESOURCE_IO)?"io port":"mmio",
-                              res->start, res->end);
+                       printk(KERN_DEBUG "bus: %02x index %x %pR\n",
+                                      busnum, j, res);
                }
        }
 
        return 0;
 }
 
-#else  /* !CONFIG_X86_64 */
-
-static int __init early_fill_mp_bus_info(void) { return 0; }
-
-#endif /* !CONFIG_X86_64 */
-
-/* common 32/64 bit code */
-
 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 
 static void enable_pci_io_ecs(void *unused)

diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
index f63e80294f22c77cbdcc8842d77f162ec93f0edd..08d8e1576240f390830b4500eac7cb4c1940fc07 100644 (file)
--- a/arch/x86/pci/bus_numa.h
+++ b/arch/x86/pci/bus_numa.h
@@ -1,5 +1,5 @@
-#ifdef CONFIG_X86_64
-
+#ifndef __BUS_NUMA_H
+#define __BUS_NUMA_H
 /*
  * sub bus (transparent) will use entres from 3 to store extra from
  * root, so need to make sure we have enough slot there, Should we

diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 5dc9e8c63fcdedb26a096d48efcf2392cd8f8209..f4e8481970bddbe2ac41e3a8f73188ec5bbe6a60 100644 (file)
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -257,10 +257,6 @@ void __init pcibios_resource_survey(void)
  */
 fs_initcall(pcibios_assign_resources);
 
-void __weak x86_pci_root_bus_res_quirks(struct pci_bus *b)
-{
-}
-
 /*
  *  If we set up a device for bus mastering, we need to check the latency
  *  timer as certain crappy BIOSes forget to set it properly.