ath9k: Remove unused AR9462 2.0 initvals
authorSujith Manoharan <c_manoha@qca.qualcomm.com>
Tue, 29 Oct 2013 06:10:06 +0000 (11:40 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 2 Dec 2013 19:24:55 +0000 (14:24 -0500)
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h

index 092b9d412e7fd7f70b5f1996b94a66703325f830..5a10dcf2adf508ec184c80fd81027958e087aec1 100644 (file)
@@ -33,13 +33,6 @@ static const u32 ar9462_modes_fast_clock_2p0[][3] = {
        {0x0000a254, 0x00000898, 0x00001130},
 };
 
-static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
-       /* Addr      allmodes  */
-       {0x00018c00, 0x18253ede},
-       {0x00018c04, 0x000801d8},
-       {0x00018c08, 0x0003780c},
-};
-
 static const u32 ar9462_2p0_baseband_postamble[][5] = {
        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
        {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a800d},
@@ -366,13 +359,6 @@ static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
        {0x00018c08, 0x0003780c},
 };
 
-static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
-       /* Addr      allmodes  */
-       {0x00018c00, 0x18212ede},
-       {0x00018c04, 0x000801d8},
-       {0x00018c08, 0x0003780c},
-};
-
 static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
        /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
        {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},