drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c files
authorBen Skeggs <bskeggs@redhat.com>
Wed, 3 Nov 2010 03:16:18 +0000 (13:16 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 3 Dec 2010 05:11:41 +0000 (15:11 +1000)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_irq.c
drivers/gpu/drm/nouveau/nouveau_object.c
drivers/gpu/drm/nouveau/nv04_graph.c
drivers/gpu/drm/nouveau/nv10_graph.c
drivers/gpu/drm/nouveau/nv20_graph.c
drivers/gpu/drm/nouveau/nv40_graph.c
drivers/gpu/drm/nouveau/nv50_graph.c

index e174479ab67544b04e23de1c37abe6be653d06a4..b19ef7fbb9dd3ec3ea8a9dd80c09eb12a8cc5f17 100644 (file)
@@ -54,6 +54,7 @@ struct nouveau_fpriv {
 #include "nouveau_drm.h"
 #include "nouveau_reg.h"
 #include "nouveau_bios.h"
+#include "nouveau_util.h"
 struct nouveau_grctx;
 
 #define MAX_NUM_DCB_ENTRIES 16
@@ -872,6 +873,7 @@ extern int  nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
                                    int (*exec)(struct nouveau_channel *,
                                                u32 class, u32 mthd, u32 data));
 extern int  nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
+extern int  nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
                                       uint32_t vram_h, uint32_t tt_h);
 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
@@ -1110,9 +1112,9 @@ extern int  nv04_graph_create_context(struct nouveau_channel *);
 extern void nv04_graph_destroy_context(struct nouveau_channel *);
 extern int  nv04_graph_load_context(struct nouveau_channel *);
 extern int  nv04_graph_unload_context(struct drm_device *);
-extern void nv04_graph_context_switch(struct drm_device *);
 extern int  nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
                                      u32 class, u32 mthd, u32 data);
+extern struct nouveau_bitfield nv04_graph_nsource[];
 
 /* nv10_graph.c */
 extern int  nv10_graph_init(struct drm_device *);
@@ -1122,8 +1124,9 @@ extern int  nv10_graph_create_context(struct nouveau_channel *);
 extern void nv10_graph_destroy_context(struct nouveau_channel *);
 extern int  nv10_graph_load_context(struct nouveau_channel *);
 extern int  nv10_graph_unload_context(struct drm_device *);
-extern void nv10_graph_context_switch(struct drm_device *);
 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
+extern struct nouveau_bitfield nv10_graph_intr[];
+extern struct nouveau_bitfield nv10_graph_nstatus[];
 
 /* nv20_graph.c */
 extern int  nv20_graph_create_context(struct nouveau_channel *);
@@ -1155,7 +1158,6 @@ extern int  nv50_graph_create_context(struct nouveau_channel *);
 extern void nv50_graph_destroy_context(struct nouveau_channel *);
 extern int  nv50_graph_load_context(struct nouveau_channel *);
 extern int  nv50_graph_unload_context(struct drm_device *);
-extern void nv50_graph_context_switch(struct drm_device *);
 extern int  nv50_grctx_init(struct nouveau_grctx *);
 extern void nv50_graph_tlb_flush(struct drm_device *dev);
 extern void nv86_graph_tlb_flush(struct drm_device *dev);
index 16f42f774a9ef5590e7f6ec75b108ef1494f602b..2ba7265bc9672fd55cf13fb33cd39da95eddb690 100644 (file)
@@ -69,910 +69,34 @@ nouveau_irq_uninstall(struct drm_device *dev)
        nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 }
 
-static struct nouveau_bitfield nstatus_names[] =
-{
-       { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
-       { NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
-       { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
-       { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
-       {}
-};
-
-static struct nouveau_bitfield nstatus_names_nv10[] =
-{
-       { NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
-       { NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
-       { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
-       { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
-       {}
-};
-
-static struct nouveau_bitfield nsource_names[] =
-{
-       { NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
-       { NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
-       { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
-       { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
-       { NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
-       { NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
-       { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
-       { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
-       { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
-       { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
-       { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
-       { NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
-       { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
-       { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
-       { NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
-       { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
-       { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
-       { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
-       { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
-       {}
-};
-
-static int
-nouveau_graph_chid_from_grctx(struct drm_device *dev)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_channel *chan;
-       unsigned long flags;
-       uint32_t inst;
-       int i;
-
-       if (dev_priv->card_type < NV_40)
-               return dev_priv->engine.fifo.channels;
-       else
-       if (dev_priv->card_type < NV_50) {
-               inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 4;
-
-               spin_lock_irqsave(&dev_priv->channels.lock, flags);
-               for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
-                       chan = dev_priv->channels.ptr[i];
-                       if (!chan || !chan->ramin_grctx)
-                               continue;
-
-                       if (inst == chan->ramin_grctx->pinst)
-                               break;
-               }
-               spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
-       } else {
-               inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 12;
-
-               spin_lock_irqsave(&dev_priv->channels.lock, flags);
-               for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
-                       chan = dev_priv->channels.ptr[i];
-                       if (!chan || !chan->ramin)
-                               continue;
-
-                       if (inst == chan->ramin->vinst)
-                               break;
-               }
-               spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
-       }
-
-
-       return i;
-}
-
-static int
-nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_engine *engine = &dev_priv->engine;
-       int channel;
-
-       if (dev_priv->card_type < NV_10)
-               channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
-       else
-       if (dev_priv->card_type < NV_40)
-               channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
-       else
-               channel = nouveau_graph_chid_from_grctx(dev);
-
-       if (channel >= engine->fifo.channels ||
-           !dev_priv->channels.ptr[channel]) {
-               NV_ERROR(dev, "AIII, invalid/inactive channel id %d\n", channel);
-               return -EINVAL;
-       }
-
-       *channel_ret = channel;
-       return 0;
-}
-
-struct nouveau_pgraph_trap {
-       int channel;
-       int class;
-       int subc, mthd, size;
-       uint32_t data, data2;
-       uint32_t nsource, nstatus;
-};
-
-static void
-nouveau_graph_trap_info(struct drm_device *dev,
-                       struct nouveau_pgraph_trap *trap)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       uint32_t address;
-
-       trap->nsource = trap->nstatus = 0;
-       if (dev_priv->card_type < NV_50) {
-               trap->nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
-               trap->nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
-       }
-
-       if (nouveau_graph_trapped_channel(dev, &trap->channel))
-               trap->channel = -1;
-       address = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
-
-       trap->mthd = address & 0x1FFC;
-       trap->data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
-       if (dev_priv->card_type < NV_10) {
-               trap->subc  = (address >> 13) & 0x7;
-       } else {
-               trap->subc  = (address >> 16) & 0x7;
-               trap->data2 = nv_rd32(dev, NV10_PGRAPH_TRAPPED_DATA_HIGH);
-       }
-
-       if (dev_priv->card_type < NV_10)
-               trap->class = nv_rd32(dev, 0x400180 + trap->subc*4) & 0xFF;
-       else if (dev_priv->card_type < NV_40)
-               trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFF;
-       else if (dev_priv->card_type < NV_50)
-               trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFFF;
-       else
-               trap->class = nv_rd32(dev, 0x400814);
-}
-
-static void
-nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
-                            struct nouveau_pgraph_trap *trap)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
-
-       if (dev_priv->card_type < NV_50) {
-               NV_INFO(dev, "%s - nSource:", id);
-               nouveau_bitfield_print(nsource_names, nsource);
-               printk(", nStatus:");
-               if (dev_priv->card_type < NV_10)
-                       nouveau_bitfield_print(nstatus_names, nstatus);
-               else
-                       nouveau_bitfield_print(nstatus_names_nv10, nstatus);
-               printk("\n");
-       }
-
-       NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
-                                       "Data 0x%08x:0x%08x\n",
-                                       id, trap->channel, trap->subc,
-                                       trap->class, trap->mthd,
-                                       trap->data2, trap->data);
-}
-
-static int
-nouveau_pgraph_intr_swmthd(struct drm_device *dev,
-                          struct nouveau_pgraph_trap *trap)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_channel *chan;
-       unsigned long flags;
-       int ret = -EINVAL;
-
-       spin_lock_irqsave(&dev_priv->channels.lock, flags);
-       if (trap->channel > 0 &&
-           trap->channel < dev_priv->engine.fifo.channels &&
-           dev_priv->channels.ptr[trap->channel]) {
-               chan = dev_priv->channels.ptr[trap->channel];
-               ret = nouveau_gpuobj_mthd_call(chan, trap->class, trap->mthd, trap->data);
-       }
-       spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
-
-       return ret;
-}
-
-static inline void
-nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
-{
-       struct nouveau_pgraph_trap trap;
-       int unhandled = 0;
-
-       nouveau_graph_trap_info(dev, &trap);
-
-       if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
-               if (nouveau_pgraph_intr_swmthd(dev, &trap))
-                       unhandled = 1;
-       } else {
-               unhandled = 1;
-       }
-
-       if (unhandled)
-               nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
-}
-
-
-static inline void
-nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
-{
-       struct nouveau_pgraph_trap trap;
-       int unhandled = 0;
-
-       nouveau_graph_trap_info(dev, &trap);
-       trap.nsource = nsource;
-
-       if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
-               if (nouveau_pgraph_intr_swmthd(dev, &trap))
-                       unhandled = 1;
-       } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
-               uint32_t v = nv_rd32(dev, 0x402000);
-               nv_wr32(dev, 0x402000, v);
-
-               /* dump the error anyway for now: it's useful for
-                  Gallium development */
-               unhandled = 1;
-       } else {
-               unhandled = 1;
-       }
-
-       if (unhandled && nouveau_ratelimit())
-               nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
-}
-
-static inline void
-nouveau_pgraph_intr_context_switch(struct drm_device *dev)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       struct nouveau_engine *engine = &dev_priv->engine;
-       uint32_t chid;
-
-       chid = engine->fifo.channel_id(dev);
-       NV_DEBUG(dev, "PGRAPH context switch interrupt channel %x\n", chid);
-
-       switch (dev_priv->card_type) {
-       case NV_04:
-               nv04_graph_context_switch(dev);
-               break;
-       case NV_10:
-               nv10_graph_context_switch(dev);
-               break;
-       default:
-               NV_ERROR(dev, "Context switch not implemented\n");
-               break;
-       }
-}
-
-static void
-nouveau_pgraph_irq_handler(struct drm_device *dev)
-{
-       uint32_t status;
-
-       while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
-               uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
-
-               if (status & NV_PGRAPH_INTR_NOTIFY) {
-                       nouveau_pgraph_intr_notify(dev, nsource);
-
-                       status &= ~NV_PGRAPH_INTR_NOTIFY;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
-               }
-
-               if (status & NV_PGRAPH_INTR_ERROR) {
-                       nouveau_pgraph_intr_error(dev, nsource);
-
-                       status &= ~NV_PGRAPH_INTR_ERROR;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
-               }
-
-               if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
-                       status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-                       nv_wr32(dev, NV03_PGRAPH_INTR,
-                                NV_PGRAPH_INTR_CONTEXT_SWITCH);
-
-                       nouveau_pgraph_intr_context_switch(dev);
-               }
-
-               if (status) {
-                       NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
-                       nv_wr32(dev, NV03_PGRAPH_INTR, status);
-               }
-
-               if ((nv_rd32(dev, NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
-                       nv_wr32(dev, NV04_PGRAPH_FIFO, 1);
-       }
-
-       nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
-}
-
-static struct nouveau_enum nv50_mp_exec_error_names[] =
-{
-       { 3, "STACK_UNDERFLOW" },
-       { 4, "QUADON_ACTIVE" },
-       { 8, "TIMEOUT" },
-       { 0x10, "INVALID_OPCODE" },
-       { 0x40, "BREAKPOINT" },
-       {}
-};
-
-static void
-nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       uint32_t units = nv_rd32(dev, 0x1540);
-       uint32_t addr, mp10, status, pc, oplow, ophigh;
-       int i;
-       int mps = 0;
-       for (i = 0; i < 4; i++) {
-               if (!(units & 1 << (i+24)))
-                       continue;
-               if (dev_priv->chipset < 0xa0)
-                       addr = 0x408200 + (tpid << 12) + (i << 7);
-               else
-                       addr = 0x408100 + (tpid << 11) + (i << 7);
-               mp10 = nv_rd32(dev, addr + 0x10);
-               status = nv_rd32(dev, addr + 0x14);
-               if (!status)
-                       continue;
-               if (display) {
-                       nv_rd32(dev, addr + 0x20);
-                       pc = nv_rd32(dev, addr + 0x24);
-                       oplow = nv_rd32(dev, addr + 0x70);
-                       ophigh= nv_rd32(dev, addr + 0x74);
-                       NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
-                                       "TP %d MP %d: ", tpid, i);
-                       nouveau_enum_print(nv50_mp_exec_error_names, status);
-                       printk(" at %06x warp %d, opcode %08x %08x\n",
-                                       pc&0xffffff, pc >> 24,
-                                       oplow, ophigh);
-               }
-               nv_wr32(dev, addr + 0x10, mp10);
-               nv_wr32(dev, addr + 0x14, 0);
-               mps++;
-       }
-       if (!mps && display)
-               NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
-                               "No MPs claiming errors?\n", tpid);
-}
-
-static void
-nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
-               uint32_t ustatus_new, int display, const char *name)
-{
-       struct drm_nouveau_private *dev_priv = dev->dev_private;
-       int tps = 0;
-       uint32_t units = nv_rd32(dev, 0x1540);
-       int i, r;
-       uint32_t ustatus_addr, ustatus;
-       for (i = 0; i < 16; i++) {
-               if (!(units & (1 << i)))
-                       continue;
-               if (dev_priv->chipset < 0xa0)
-                       ustatus_addr = ustatus_old + (i << 12);
-               else
-                       ustatus_addr = ustatus_new + (i << 11);
-               ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
-               if (!ustatus)
-                       continue;
-               tps++;
-               switch (type) {
-               case 6: /* texture error... unknown for now */
-                       nv50_fb_vm_trap(dev, display, name);
-                       if (display) {
-                               NV_ERROR(dev, "magic set %d:\n", i);
-                               for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
-                                       NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
-                                               nv_rd32(dev, r));
-                       }
-                       break;
-               case 7: /* MP error */
-                       if (ustatus & 0x00010000) {
-                               nv50_pgraph_mp_trap(dev, i, display);
-                               ustatus &= ~0x00010000;
-                       }
-                       break;
-               case 8: /* TPDMA error */
-                       {
-                       uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
-                       uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
-                       uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
-                       uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
-                       uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
-                       uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
-                       uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
-                       nv50_fb_vm_trap(dev, display, name);
-                       /* 2d engine destination */
-                       if (ustatus & 0x00000010) {
-                               if (display) {
-                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
-                                                       i, e14, e10);
-                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
-                                                       i, e0c, e18, e1c, e20, e24);
-                               }
-                               ustatus &= ~0x00000010;
-                       }
-                       /* Render target */
-                       if (ustatus & 0x00000040) {
-                               if (display) {
-                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
-                                                       i, e14, e10);
-                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
-                                                       i, e0c, e18, e1c, e20, e24);
-                               }
-                               ustatus &= ~0x00000040;
-                       }
-                       /* CUDA memory: l[], g[] or stack. */
-                       if (ustatus & 0x00000080) {
-                               if (display) {
-                                       if (e18 & 0x80000000) {
-                                               /* g[] read fault? */
-                                               NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
-                                                               i, e14, e10 | ((e18 >> 24) & 0x1f));
-                                               e18 &= ~0x1f000000;
-                                       } else if (e18 & 0xc) {
-                                               /* g[] write fault? */
-                                               NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
-                                                               i, e14, e10 | ((e18 >> 7) & 0x1f));
-                                               e18 &= ~0x00000f80;
-                                       } else {
-                                               NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
-                                                               i, e14, e10);
-                                       }
-                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
-                                                       i, e0c, e18, e1c, e20, e24);
-                               }
-                               ustatus &= ~0x00000080;
-                       }
-                       }
-                       break;
-               }
-               if (ustatus) {
-                       if (display)
-                               NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
-               }
-               nv_wr32(dev, ustatus_addr, 0xc0000000);
-       }
-
-       if (!tps && display)
-               NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
-}
-
-static void
-nv50_pgraph_trap_handler(struct drm_device *dev)
-{
-       struct nouveau_pgraph_trap trap;
-       uint32_t status = nv_rd32(dev, 0x400108);
-       uint32_t ustatus;
-       int display = nouveau_ratelimit();
-
-
-       if (!status && display) {
-               nouveau_graph_trap_info(dev, &trap);
-               nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
-               NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
-       }
-
-       /* DISPATCH: Relays commands to other units and handles NOTIFY,
-        * COND, QUERY. If you get a trap from it, the command is still stuck
-        * in DISPATCH and you need to do something about it. */
-       if (status & 0x001) {
-               ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
-               if (!ustatus && display) {
-                       NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
-               }
-
-               /* Known to be triggered by screwed up NOTIFY and COND... */
-               if (ustatus & 0x00000001) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
-                       nv_wr32(dev, 0x400500, 0);
-                       if (nv_rd32(dev, 0x400808) & 0x80000000) {
-                               if (display) {
-                                       if (nouveau_graph_trapped_channel(dev, &trap.channel))
-                                               trap.channel = -1;
-                                       trap.class = nv_rd32(dev, 0x400814);
-                                       trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
-                                       trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
-                                       trap.data = nv_rd32(dev, 0x40080c);
-                                       trap.data2 = nv_rd32(dev, 0x400810);
-                                       nouveau_graph_dump_trap_info(dev,
-                                                       "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
-                                       NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
-                                       NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
-                               }
-                               nv_wr32(dev, 0x400808, 0);
-                       } else if (display) {
-                               NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
-                       }
-                       nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
-                       nv_wr32(dev, 0x400848, 0);
-                       ustatus &= ~0x00000001;
-               }
-               if (ustatus & 0x00000002) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
-                       nv_wr32(dev, 0x400500, 0);
-                       if (nv_rd32(dev, 0x40084c) & 0x80000000) {
-                               if (display) {
-                                       if (nouveau_graph_trapped_channel(dev, &trap.channel))
-                                               trap.channel = -1;
-                                       trap.class = nv_rd32(dev, 0x400814);
-                                       trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
-                                       trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
-                                       trap.data = nv_rd32(dev, 0x40085c);
-                                       trap.data2 = 0;
-                                       nouveau_graph_dump_trap_info(dev,
-                                                       "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
-                                       NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
-                               }
-                               nv_wr32(dev, 0x40084c, 0);
-                       } else if (display) {
-                               NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
-                       }
-                       ustatus &= ~0x00000002;
-               }
-               if (ustatus && display)
-                       NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
-               nv_wr32(dev, 0x400804, 0xc0000000);
-               nv_wr32(dev, 0x400108, 0x001);
-               status &= ~0x001;
-       }
-
-       /* TRAPs other than dispatch use the "normal" trap regs. */
-       if (status && display) {
-               nouveau_graph_trap_info(dev, &trap);
-               nouveau_graph_dump_trap_info(dev,
-                               "PGRAPH_TRAP", &trap);
-       }
-
-       /* M2MF: Memory to memory copy engine. */
-       if (status & 0x002) {
-               ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
-               if (!ustatus && display) {
-                       NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
-               }
-               if (ustatus & 0x00000001) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
-                       ustatus &= ~0x00000001;
-               }
-               if (ustatus & 0x00000002) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
-                       ustatus &= ~0x00000002;
-               }
-               if (ustatus & 0x00000004) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
-                       ustatus &= ~0x00000004;
-               }
-               NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
-                               nv_rd32(dev, 0x406804),
-                               nv_rd32(dev, 0x406808),
-                               nv_rd32(dev, 0x40680c),
-                               nv_rd32(dev, 0x406810));
-               if (ustatus && display)
-                       NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
-               /* No sane way found yet -- just reset the bugger. */
-               nv_wr32(dev, 0x400040, 2);
-               nv_wr32(dev, 0x400040, 0);
-               nv_wr32(dev, 0x406800, 0xc0000000);
-               nv_wr32(dev, 0x400108, 0x002);
-               status &= ~0x002;
-       }
-
-       /* VFETCH: Fetches data from vertex buffers. */
-       if (status & 0x004) {
-               ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
-               if (!ustatus && display) {
-                       NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
-               }
-               if (ustatus & 0x00000001) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
-                       NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
-                                       nv_rd32(dev, 0x400c00),
-                                       nv_rd32(dev, 0x400c08),
-                                       nv_rd32(dev, 0x400c0c),
-                                       nv_rd32(dev, 0x400c10));
-                       ustatus &= ~0x00000001;
-               }
-               if (ustatus && display)
-                       NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
-               nv_wr32(dev, 0x400c04, 0xc0000000);
-               nv_wr32(dev, 0x400108, 0x004);
-               status &= ~0x004;
-       }
-
-       /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
-       if (status & 0x008) {
-               ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
-               if (!ustatus && display) {
-                       NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
-               }
-               if (ustatus & 0x00000001) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
-                       NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
-                                       nv_rd32(dev, 0x401804),
-                                       nv_rd32(dev, 0x401808),
-                                       nv_rd32(dev, 0x40180c),
-                                       nv_rd32(dev, 0x401810));
-                       ustatus &= ~0x00000001;
-               }
-               if (ustatus && display)
-                       NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
-               /* No sane way found yet -- just reset the bugger. */
-               nv_wr32(dev, 0x400040, 0x80);
-               nv_wr32(dev, 0x400040, 0);
-               nv_wr32(dev, 0x401800, 0xc0000000);
-               nv_wr32(dev, 0x400108, 0x008);
-               status &= ~0x008;
-       }
-
-       /* CCACHE: Handles code and c[] caches and fills them. */
-       if (status & 0x010) {
-               ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
-               if (!ustatus && display) {
-                       NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
-               }
-               if (ustatus & 0x00000001) {
-                       nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
-                       NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
-                                       nv_rd32(dev, 0x405800),
-                                       nv_rd32(dev, 0x405804),
-                                       nv_rd32(dev, 0x405808),
-                                       nv_rd32(dev, 0x40580c),
-                                       nv_rd32(dev, 0x405810),
-                                       nv_rd32(dev, 0x405814),
-                                       nv_rd32(dev, 0x40581c));
-                       ustatus &= ~0x00000001;
-               }
-               if (ustatus && display)
-                       NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
-               nv_wr32(dev, 0x405018, 0xc0000000);
-               nv_wr32(dev, 0x400108, 0x010);
-               status &= ~0x010;
-       }
-
-       /* Unknown, not seen yet... 0x402000 is the only trap status reg
-        * remaining, so try to handle it anyway. Perhaps related to that
-        * unknown DMA slot on tesla? */
-       if (status & 0x20) {
-               nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
-               ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
-               if (display)
-                       NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
-               nv_wr32(dev, 0x402000, 0xc0000000);
-               /* no status modifiction on purpose */
-       }
-
-       /* TEXTURE: CUDA texturing units */
-       if (status & 0x040) {
-               nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
-                               "PGRAPH_TRAP_TEXTURE");
-               nv_wr32(dev, 0x400108, 0x040);
-               status &= ~0x040;
-       }
-
-       /* MP: CUDA execution engines. */
-       if (status & 0x080) {
-               nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
-                               "PGRAPH_TRAP_MP");
-               nv_wr32(dev, 0x400108, 0x080);
-               status &= ~0x080;
-       }
-
-       /* TPDMA:  Handles TP-initiated uncached memory accesses:
-        * l[], g[], stack, 2d surfaces, render targets. */
-       if (status & 0x100) {
-               nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
-                               "PGRAPH_TRAP_TPDMA");
-               nv_wr32(dev, 0x400108, 0x100);
-               status &= ~0x100;
-       }
-
-       if (status) {
-               if (display)
-                       NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
-                               status);
-               nv_wr32(dev, 0x400108, status);
-       }
-}
-
-/* There must be a *lot* of these. Will take some time to gather them up. */
-static struct nouveau_enum nv50_data_error_names[] =
-{
-       { 4,    "INVALID_VALUE" },
-       { 5,    "INVALID_ENUM" },
-       { 8,    "INVALID_OBJECT" },
-       { 0xc,  "INVALID_BITFIELD" },
-       { 0x28, "MP_NO_REG_SPACE" },
-       { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
-       {}
-};
-
-static void
-nv50_pgraph_irq_handler(struct drm_device *dev)
-{
-       struct nouveau_pgraph_trap trap;
-       int unhandled = 0;
-       uint32_t status;
-
-       while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
-               /* NOTIFY: You've set a NOTIFY an a command and it's done. */
-               if (status & 0x00000001) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_NOTIFY", &trap);
-                       status &= ~0x00000001;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
-               }
-
-               /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
-                * when you write 0x200 to 0x50c0 method 0x31c. */
-               if (status & 0x00000002) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_COMPUTE_QUERY", &trap);
-                       status &= ~0x00000002;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
-               }
-
-               /* Unknown, never seen: 0x4 */
-
-               /* ILLEGAL_MTHD: You used a wrong method for this class. */
-               if (status & 0x00000010) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_pgraph_intr_swmthd(dev, &trap))
-                               unhandled = 1;
-                       if (unhandled && nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_ILLEGAL_MTHD", &trap);
-                       status &= ~0x00000010;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
-               }
-
-               /* ILLEGAL_CLASS: You used a wrong class. */
-               if (status & 0x00000020) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_ILLEGAL_CLASS", &trap);
-                       status &= ~0x00000020;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
-               }
-
-               /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
-               if (status & 0x00000040) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_DOUBLE_NOTIFY", &trap);
-                       status &= ~0x00000040;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
-               }
-
-               /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
-               if (status & 0x00001000) {
-                       nv_wr32(dev, 0x400500, 0x00000000);
-                       nv_wr32(dev, NV03_PGRAPH_INTR,
-                               NV_PGRAPH_INTR_CONTEXT_SWITCH);
-                       nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
-                               NV40_PGRAPH_INTR_EN) &
-                               ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
-                       nv_wr32(dev, 0x400500, 0x00010001);
-
-                       nv50_graph_context_switch(dev);
-
-                       status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
-               }
-
-               /* BUFFER_NOTIFY: Your m2mf transfer finished */
-               if (status & 0x00010000) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_BUFFER_NOTIFY", &trap);
-                       status &= ~0x00010000;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
-               }
-
-               /* DATA_ERROR: Invalid value for this method, or invalid
-                * state in current PGRAPH context for this operation */
-               if (status & 0x00100000) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit()) {
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_DATA_ERROR", &trap);
-                               NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
-                               nouveau_enum_print(nv50_data_error_names,
-                                                  nv_rd32(dev, 0x400110));
-                               printk("\n");
-                       }
-                       status &= ~0x00100000;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
-               }
-
-               /* TRAP: Something bad happened in the middle of command
-                * execution.  Has a billion types, subtypes, and even
-                * subsubtypes. */
-               if (status & 0x00200000) {
-                       nv50_pgraph_trap_handler(dev);
-                       status &= ~0x00200000;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
-               }
-
-               /* Unknown, never seen: 0x00400000 */
-
-               /* SINGLE_STEP: Happens on every method if you turned on
-                * single stepping in 40008c */
-               if (status & 0x01000000) {
-                       nouveau_graph_trap_info(dev, &trap);
-                       if (nouveau_ratelimit())
-                               nouveau_graph_dump_trap_info(dev,
-                                               "PGRAPH_SINGLE_STEP", &trap);
-                       status &= ~0x01000000;
-                       nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
-               }
-
-               /* 0x02000000 happens when you pause a ctxprog...
-                * but the only way this can happen that I know is by
-                * poking the relevant MMIO register, and we don't
-                * do that. */
-
-               if (status) {
-                       NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
-                               status);
-                       nv_wr32(dev, NV03_PGRAPH_INTR, status);
-               }
-
-               {
-                       const int isb = (1 << 16) | (1 << 0);
-
-                       if ((nv_rd32(dev, 0x400500) & isb) != isb)
-                               nv_wr32(dev, 0x400500,
-                                       nv_rd32(dev, 0x400500) | isb);
-               }
-       }
-
-       nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
-       if (nv_rd32(dev, 0x400824) & (1 << 31))
-               nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
-}
-
 irqreturn_t
 nouveau_irq_handler(DRM_IRQ_ARGS)
 {
        struct drm_device *dev = (struct drm_device *)arg;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        unsigned long flags;
-       u32 status;
+       u32 stat;
        int i;
 
-       status = nv_rd32(dev, NV03_PMC_INTR_0);
-       if (!status)
+       stat = nv_rd32(dev, NV03_PMC_INTR_0);
+       if (!stat)
                return IRQ_NONE;
 
        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
-
-       if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
-               if (dev_priv->card_type >= NV_50)
-                       nv50_pgraph_irq_handler(dev);
-               else
-                       nouveau_pgraph_irq_handler(dev);
-
-               status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
-       }
-
-       for (i = 0; i < 32 && status; i++) {
-               if (!(status & (1 << i)) || !dev_priv->irq_handler[i])
+       for (i = 0; i < 32 && stat; i++) {
+               if (!(stat & (1 << i)) || !dev_priv->irq_handler[i])
                        continue;
 
                dev_priv->irq_handler[i](dev);
-               status &= ~(1 << i);
+               stat &= ~(1 << i);
        }
 
-       if (status)
-               NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status);
-
-       spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
-
        if (dev_priv->msi_enabled)
                nv_wr08(dev, 0x00088068, 0xff);
+       spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
+       if (stat && nouveau_ratelimit())
+               NV_ERROR(dev, "PMC - unhandled INTR 0x%08x\n", stat);
        return IRQ_HANDLED;
 }
 
index 54078186fe655a5399f76abd19171a9aa7adec69..94429553433cafe26ecac134e303dc456d0471d2 100644 (file)
@@ -113,6 +113,24 @@ nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
        return -ENOENT;
 }
 
+int
+nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
+                         u32 class, u32 mthd, u32 data)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_channel *chan = NULL;
+       unsigned long flags;
+       int ret = -EINVAL;
+
+       spin_lock_irqsave(&dev_priv->channels.lock, flags);
+       if (chid > 0 && chid < dev_priv->engine.fifo.channels)
+               chan = dev_priv->channels.ptr[chid];
+       if (chan)
+               ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
+       spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+       return ret;
+}
+
 /* NVidia uses context objects to drive drawing operations.
 
    Context objects can be selected into 8 subchannels in the FIFO,
index 239519aefce6208da8bd0120356855ea71ef97f1..0bc616d35eb6ac11649e1c4b5d22dc2185974b17 100644 (file)
 #include "nouveau_drm.h"
 #include "nouveau_drv.h"
 #include "nouveau_hw.h"
+#include "nouveau_util.h"
 
-static int nv04_graph_register(struct drm_device *dev);
+static int  nv04_graph_register(struct drm_device *dev);
+static void nv04_graph_isr(struct drm_device *dev);
 
 static uint32_t nv04_graph_ctx_regs[] = {
        0x0040053c,
@@ -363,7 +365,7 @@ nv04_graph_channel(struct drm_device *dev)
        return dev_priv->channels.ptr[chid];
 }
 
-void
+static void
 nv04_graph_context_switch(struct drm_device *dev)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -498,6 +500,7 @@ int nv04_graph_init(struct drm_device *dev)
                return ret;
 
        /* Enable PGRAPH interrupts */
+       nouveau_irq_register(dev, 12, nv04_graph_isr);
        nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
        nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
@@ -533,6 +536,8 @@ int nv04_graph_init(struct drm_device *dev)
 
 void nv04_graph_takedown(struct drm_device *dev)
 {
+       nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
+       nouveau_irq_unregister(dev, 12);
 }
 
 void
@@ -1224,3 +1229,89 @@ nv04_graph_register(struct drm_device *dev)
        dev_priv->engine.graph.registered = true;
        return 0;
 };
+
+static struct nouveau_bitfield nv04_graph_intr[] = {
+       { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
+       {}
+};
+
+static struct nouveau_bitfield nv04_graph_nstatus[] =
+{
+       { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
+       { NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
+       { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
+       { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
+       {}
+};
+
+struct nouveau_bitfield nv04_graph_nsource[] =
+{
+       { NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
+       { NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
+       { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
+       { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
+       { NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
+       { NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
+       { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
+       { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
+       { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
+       { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
+       { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
+       { NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
+       { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
+       { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
+       { NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
+       { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
+       { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
+       { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
+       { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
+       {}
+};
+
+static void
+nv04_graph_isr(struct drm_device *dev)
+{
+       u32 stat;
+
+       while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
+               u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
+               u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
+               u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
+               u32 chid = (addr & 0x0f000000) >> 24;
+               u32 subc = (addr & 0x0000e000) >> 13;
+               u32 mthd = (addr & 0x00001ffc);
+               u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
+               u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
+               u32 show = stat;
+
+               if (stat & NV_PGRAPH_INTR_NOTIFY) {
+                       if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
+                               if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
+                                       show &= ~NV_PGRAPH_INTR_NOTIFY;
+                       }
+               }
+
+               if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
+                       nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+                       stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+                       show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+                       nv04_graph_context_switch(dev);
+               }
+
+               nv_wr32(dev, NV03_PGRAPH_INTR, stat);
+               nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
+
+               if (show && nouveau_ratelimit()) {
+                       NV_INFO(dev, "PGRAPH -");
+                       nouveau_bitfield_print(nv04_graph_intr, show);
+                       printk(" nsource:");
+                       nouveau_bitfield_print(nv04_graph_nsource, nsource);
+                       printk(" nstatus:");
+                       nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
+                                    "mthd 0x%04x data 0x%08x\n",
+                               chid, subc, class, mthd, data);
+               }
+       }
+}
index 1cd141edca04d51da796f79ebfc4c5a2d7bbc899..536b39e4a9e2661f31cf386e10a37c1dea310d9f 100644 (file)
 #include "drm.h"
 #include "nouveau_drm.h"
 #include "nouveau_drv.h"
+#include "nouveau_util.h"
 
-static int nv10_graph_register(struct drm_device *);
+static int  nv10_graph_register(struct drm_device *);
+static void nv10_graph_isr(struct drm_device *);
 
 #define NV10_FIFO_NUMBER 32
 
@@ -788,7 +790,7 @@ nv10_graph_unload_context(struct drm_device *dev)
        return 0;
 }
 
-void
+static void
 nv10_graph_context_switch(struct drm_device *dev)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -924,6 +926,7 @@ int nv10_graph_init(struct drm_device *dev)
        if (ret)
                return ret;
 
+       nouveau_irq_register(dev, 12, nv10_graph_isr);
        nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
        nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
@@ -966,6 +969,8 @@ int nv10_graph_init(struct drm_device *dev)
 
 void nv10_graph_takedown(struct drm_device *dev)
 {
+       nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
+       nouveau_irq_unregister(dev, 12);
 }
 
 static int
@@ -1117,3 +1122,66 @@ nv10_graph_register(struct drm_device *dev)
        dev_priv->engine.graph.registered = true;
        return 0;
 }
+
+struct nouveau_bitfield nv10_graph_intr[] = {
+       { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
+       { NV_PGRAPH_INTR_ERROR,  "ERROR"  },
+       {}
+};
+
+struct nouveau_bitfield nv10_graph_nstatus[] =
+{
+       { NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
+       { NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
+       { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
+       { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" },
+       {}
+};
+
+static void
+nv10_graph_isr(struct drm_device *dev)
+{
+       u32 stat;
+
+       while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
+               u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
+               u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
+               u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
+               u32 chid = (addr & 0x01f00000) >> 20;
+               u32 subc = (addr & 0x00070000) >> 16;
+               u32 mthd = (addr & 0x00001ffc);
+               u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
+               u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
+               u32 show = stat;
+
+               if (stat & NV_PGRAPH_INTR_ERROR) {
+                       if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
+                               if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
+                                       show &= ~NV_PGRAPH_INTR_ERROR;
+                       }
+               }
+
+               if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
+                       nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+                       stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+                       show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+                       nv10_graph_context_switch(dev);
+               }
+
+               nv_wr32(dev, NV03_PGRAPH_INTR, stat);
+               nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
+
+               if (show && nouveau_ratelimit()) {
+                       NV_INFO(dev, "PGRAPH -");
+                       nouveau_bitfield_print(nv10_graph_intr, show);
+                       printk(" nsource:");
+                       nouveau_bitfield_print(nv04_graph_nsource, nsource);
+                       printk(" nstatus:");
+                       nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
+                                    "mthd 0x%04x data 0x%08x\n",
+                               chid, subc, class, mthd, data);
+               }
+       }
+}
index bd065c2fcba4f244d28564d500730ec530d11de6..8464b76798d5e4746af344ef260526a4b97fdee9 100644 (file)
@@ -34,6 +34,7 @@
 
 static int nv20_graph_register(struct drm_device *);
 static int nv30_graph_register(struct drm_device *);
+static void nv20_graph_isr(struct drm_device *);
 
 static void
 nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
@@ -584,6 +585,7 @@ nv20_graph_init(struct drm_device *dev)
                return ret;
        }
 
+       nouveau_irq_register(dev, 12, nv20_graph_isr);
        nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
        nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
@@ -661,6 +663,9 @@ nv20_graph_takedown(struct drm_device *dev)
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 
+       nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
+       nouveau_irq_unregister(dev, 12);
+
        nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
 }
 
@@ -712,6 +717,7 @@ nv30_graph_init(struct drm_device *dev)
        nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
                     pgraph->ctx_table->pinst >> 4);
 
+       nouveau_irq_register(dev, 12, nv20_graph_isr);
        nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
        nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
@@ -850,3 +856,44 @@ nv30_graph_register(struct drm_device *dev)
        dev_priv->engine.graph.registered = true;
        return 0;
 }
+
+static void
+nv20_graph_isr(struct drm_device *dev)
+{
+       u32 stat;
+
+       while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
+               u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
+               u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
+               u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
+               u32 chid = (addr & 0x01f00000) >> 20;
+               u32 subc = (addr & 0x00070000) >> 16;
+               u32 mthd = (addr & 0x00001ffc);
+               u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
+               u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
+               u32 show = stat;
+
+               if (stat & NV_PGRAPH_INTR_ERROR) {
+                       if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
+                               if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
+                                       show &= ~NV_PGRAPH_INTR_ERROR;
+                       }
+               }
+
+               nv_wr32(dev, NV03_PGRAPH_INTR, stat);
+               nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
+
+               if (show && nouveau_ratelimit()) {
+                       NV_INFO(dev, "PGRAPH -");
+                       nouveau_bitfield_print(nv10_graph_intr, show);
+                       printk(" nsource:");
+                       nouveau_bitfield_print(nv04_graph_nsource, nsource);
+                       printk(" nstatus:");
+                       nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
+                                    "mthd 0x%04x data 0x%08x\n",
+                               chid, subc, class, mthd, data);
+               }
+       }
+}
index 7a51608b55ba4effceb2ff6214a14993613e244e..0618846a97ce4292b9bd21625cca36e3d090a521 100644 (file)
@@ -30,6 +30,7 @@
 #include "nouveau_grctx.h"
 
 static int nv40_graph_register(struct drm_device *);
+static void nv40_graph_isr(struct drm_device *);
 
 struct nouveau_channel *
 nv40_graph_channel(struct drm_device *dev)
@@ -277,6 +278,7 @@ nv40_graph_init(struct drm_device *dev)
        /* No context present currently */
        nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 
+       nouveau_irq_register(dev, 12, nv40_graph_isr);
        nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
        nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 
@@ -408,6 +410,7 @@ nv40_graph_init(struct drm_device *dev)
 
 void nv40_graph_takedown(struct drm_device *dev)
 {
+       nouveau_irq_unregister(dev, 12);
 }
 
 static int
@@ -449,3 +452,69 @@ nv40_graph_register(struct drm_device *dev)
        dev_priv->engine.graph.registered = true;
        return 0;
 }
+
+static int
+nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_channel *chan;
+       unsigned long flags;
+       int i;
+
+       spin_lock_irqsave(&dev_priv->channels.lock, flags);
+       for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
+               chan = dev_priv->channels.ptr[i];
+               if (!chan || !chan->ramin_grctx)
+                       continue;
+
+               if (inst == chan->ramin_grctx->pinst)
+                       break;
+       }
+       spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+       return i;
+}
+
+static void
+nv40_graph_isr(struct drm_device *dev)
+{
+       u32 stat;
+
+       while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
+               u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
+               u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
+               u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
+               u32 chid = nv40_graph_isr_chid(dev, inst);
+               u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
+               u32 subc = (addr & 0x00070000) >> 16;
+               u32 mthd = (addr & 0x00001ffc);
+               u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
+               u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
+               u32 show = stat;
+
+               if (stat & NV_PGRAPH_INTR_ERROR) {
+                       if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
+                               if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
+                                       show &= ~NV_PGRAPH_INTR_ERROR;
+                       } else
+                       if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
+                               nv_mask(dev, 0x402000, 0, 0);
+                       }
+               }
+
+               nv_wr32(dev, NV03_PGRAPH_INTR, stat);
+               nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
+
+               if (show && nouveau_ratelimit()) {
+                       NV_INFO(dev, "PGRAPH -");
+                       nouveau_bitfield_print(nv10_graph_intr, show);
+                       printk(" nsource:");
+                       nouveau_bitfield_print(nv04_graph_nsource, nsource);
+                       printk(" nstatus:");
+                       nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
+                                    "class 0x%04x mthd 0x%04x data 0x%08x\n",
+                               chid, inst, subc, class, mthd, data);
+               }
+       }
+}
index 6785269f778aaf147462c50112781fe8500694da..b3900788c66d2103bb947b7926926063c067a3eb 100644 (file)
@@ -32,7 +32,8 @@
 #include "nouveau_dma.h"
 #include "nv50_evo.h"
 
-static int nv50_graph_register(struct drm_device *);
+static int  nv50_graph_register(struct drm_device *);
+static void nv50_graph_isr(struct drm_device *);
 
 static void
 nv50_graph_init_reset(struct drm_device *dev)
@@ -50,6 +51,7 @@ nv50_graph_init_intr(struct drm_device *dev)
 {
        NV_DEBUG(dev, "\n");
 
+       nouveau_irq_register(dev, 12, nv50_graph_isr);
        nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
        nv_wr32(dev, 0x400138, 0xffffffff);
        nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
@@ -165,6 +167,8 @@ void
 nv50_graph_takedown(struct drm_device *dev)
 {
        NV_DEBUG(dev, "\n");
+       nv_wr32(dev, 0x40013c, 0x00000000);
+       nouveau_irq_unregister(dev, 12);
 }
 
 void
@@ -324,7 +328,7 @@ nv50_graph_unload_context(struct drm_device *dev)
        return 0;
 }
 
-void
+static void
 nv50_graph_context_switch(struct drm_device *dev)
 {
        uint32_t inst;
@@ -512,3 +516,495 @@ nv86_graph_tlb_flush(struct drm_device *dev)
        nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 }
+
+static struct nouveau_enum nv50_mp_exec_error_names[] =
+{
+       { 3, "STACK_UNDERFLOW" },
+       { 4, "QUADON_ACTIVE" },
+       { 8, "TIMEOUT" },
+       { 0x10, "INVALID_OPCODE" },
+       { 0x40, "BREAKPOINT" },
+       {}
+};
+
+static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
+       { 0x00000001, "NOTIFY" },
+       { 0x00000002, "IN" },
+       { 0x00000004, "OUT" },
+       {}
+};
+
+static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
+       { 0x00000001, "FAULT" },
+       {}
+};
+
+static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
+       { 0x00000001, "FAULT" },
+       {}
+};
+
+static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
+       { 0x00000001, "FAULT" },
+       {}
+};
+
+/* There must be a *lot* of these. Will take some time to gather them up. */
+static struct nouveau_enum nv50_data_error_names[] = {
+       { 4,    "INVALID_VALUE" },
+       { 5,    "INVALID_ENUM" },
+       { 8,    "INVALID_OBJECT" },
+       { 0xc,  "INVALID_BITFIELD" },
+       { 0x28, "MP_NO_REG_SPACE" },
+       { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
+       {}
+};
+
+static struct nouveau_bitfield nv50_graph_intr[] = {
+       { 0x00000001, "NOTIFY" },
+       { 0x00000002, "COMPUTE_QUERY" },
+       { 0x00000010, "ILLEGAL_MTHD" },
+       { 0x00000020, "ILLEGAL_CLASS" },
+       { 0x00000040, "DOUBLE_NOTIFY" },
+       { 0x00001000, "CONTEXT_SWITCH" },
+       { 0x00010000, "BUFFER_NOTIFY" },
+       { 0x00100000, "DATA_ERROR" },
+       { 0x00200000, "TRAP" },
+       { 0x01000000, "SINGLE_STEP" },
+       {}
+};
+
+static void
+nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       uint32_t units = nv_rd32(dev, 0x1540);
+       uint32_t addr, mp10, status, pc, oplow, ophigh;
+       int i;
+       int mps = 0;
+       for (i = 0; i < 4; i++) {
+               if (!(units & 1 << (i+24)))
+                       continue;
+               if (dev_priv->chipset < 0xa0)
+                       addr = 0x408200 + (tpid << 12) + (i << 7);
+               else
+                       addr = 0x408100 + (tpid << 11) + (i << 7);
+               mp10 = nv_rd32(dev, addr + 0x10);
+               status = nv_rd32(dev, addr + 0x14);
+               if (!status)
+                       continue;
+               if (display) {
+                       nv_rd32(dev, addr + 0x20);
+                       pc = nv_rd32(dev, addr + 0x24);
+                       oplow = nv_rd32(dev, addr + 0x70);
+                       ophigh= nv_rd32(dev, addr + 0x74);
+                       NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
+                                       "TP %d MP %d: ", tpid, i);
+                       nouveau_enum_print(nv50_mp_exec_error_names, status);
+                       printk(" at %06x warp %d, opcode %08x %08x\n",
+                                       pc&0xffffff, pc >> 24,
+                                       oplow, ophigh);
+               }
+               nv_wr32(dev, addr + 0x10, mp10);
+               nv_wr32(dev, addr + 0x14, 0);
+               mps++;
+       }
+       if (!mps && display)
+               NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
+                               "No MPs claiming errors?\n", tpid);
+}
+
+static void
+nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
+               uint32_t ustatus_new, int display, const char *name)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       int tps = 0;
+       uint32_t units = nv_rd32(dev, 0x1540);
+       int i, r;
+       uint32_t ustatus_addr, ustatus;
+       for (i = 0; i < 16; i++) {
+               if (!(units & (1 << i)))
+                       continue;
+               if (dev_priv->chipset < 0xa0)
+                       ustatus_addr = ustatus_old + (i << 12);
+               else
+                       ustatus_addr = ustatus_new + (i << 11);
+               ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
+               if (!ustatus)
+                       continue;
+               tps++;
+               switch (type) {
+               case 6: /* texture error... unknown for now */
+                       nv50_fb_vm_trap(dev, display, name);
+                       if (display) {
+                               NV_ERROR(dev, "magic set %d:\n", i);
+                               for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
+                                       NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
+                                               nv_rd32(dev, r));
+                       }
+                       break;
+               case 7: /* MP error */
+                       if (ustatus & 0x00010000) {
+                               nv50_pgraph_mp_trap(dev, i, display);
+                               ustatus &= ~0x00010000;
+                       }
+                       break;
+               case 8: /* TPDMA error */
+                       {
+                       uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
+                       uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
+                       uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
+                       uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
+                       uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
+                       uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
+                       uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
+                       nv50_fb_vm_trap(dev, display, name);
+                       /* 2d engine destination */
+                       if (ustatus & 0x00000010) {
+                               if (display) {
+                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
+                                                       i, e14, e10);
+                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
+                                                       i, e0c, e18, e1c, e20, e24);
+                               }
+                               ustatus &= ~0x00000010;
+                       }
+                       /* Render target */
+                       if (ustatus & 0x00000040) {
+                               if (display) {
+                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
+                                                       i, e14, e10);
+                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
+                                                       i, e0c, e18, e1c, e20, e24);
+                               }
+                               ustatus &= ~0x00000040;
+                       }
+                       /* CUDA memory: l[], g[] or stack. */
+                       if (ustatus & 0x00000080) {
+                               if (display) {
+                                       if (e18 & 0x80000000) {
+                                               /* g[] read fault? */
+                                               NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
+                                                               i, e14, e10 | ((e18 >> 24) & 0x1f));
+                                               e18 &= ~0x1f000000;
+                                       } else if (e18 & 0xc) {
+                                               /* g[] write fault? */
+                                               NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
+                                                               i, e14, e10 | ((e18 >> 7) & 0x1f));
+                                               e18 &= ~0x00000f80;
+                                       } else {
+                                               NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
+                                                               i, e14, e10);
+                                       }
+                                       NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
+                                                       i, e0c, e18, e1c, e20, e24);
+                               }
+                               ustatus &= ~0x00000080;
+                       }
+                       }
+                       break;
+               }
+               if (ustatus) {
+                       if (display)
+                               NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
+               }
+               nv_wr32(dev, ustatus_addr, 0xc0000000);
+       }
+
+       if (!tps && display)
+               NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
+}
+
+static int
+nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
+{
+       u32 status = nv_rd32(dev, 0x400108);
+       u32 ustatus;
+
+       if (!status && display) {
+               NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
+               return 1;
+       }
+
+       /* DISPATCH: Relays commands to other units and handles NOTIFY,
+        * COND, QUERY. If you get a trap from it, the command is still stuck
+        * in DISPATCH and you need to do something about it. */
+       if (status & 0x001) {
+               ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
+               if (!ustatus && display) {
+                       NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
+               }
+
+               nv_wr32(dev, 0x400500, 0x00000000);
+
+               /* Known to be triggered by screwed up NOTIFY and COND... */
+               if (ustatus & 0x00000001) {
+                       u32 addr = nv_rd32(dev, 0x400808);
+                       u32 subc = (addr & 0x00070000) >> 16;
+                       u32 mthd = (addr & 0x00001ffc);
+                       u32 datal = nv_rd32(dev, 0x40080c);
+                       u32 datah = nv_rd32(dev, 0x400810);
+                       u32 class = nv_rd32(dev, 0x400814);
+                       u32 r848 = nv_rd32(dev, 0x400848);
+
+                       NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
+                       if (display && (addr & 0x80000000)) {
+                               NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
+                                            "subc %d class 0x%04x mthd 0x%04x "
+                                            "data 0x%08x%08x "
+                                            "400808 0x%08x 400848 0x%08x\n",
+                                       chid, inst, subc, class, mthd, datah,
+                                       datal, addr, r848);
+                       } else
+                       if (display) {
+                               NV_INFO(dev, "PGRAPH - no stuck command?\n");
+                       }
+
+                       nv_wr32(dev, 0x400808, 0);
+                       nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
+                       nv_wr32(dev, 0x400848, 0);
+                       ustatus &= ~0x00000001;
+               }
+
+               if (ustatus & 0x00000002) {
+                       u32 addr = nv_rd32(dev, 0x40084c);
+                       u32 subc = (addr & 0x00070000) >> 16;
+                       u32 mthd = (addr & 0x00001ffc);
+                       u32 data = nv_rd32(dev, 0x40085c);
+                       u32 class = nv_rd32(dev, 0x400814);
+
+                       NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
+                       if (display && (addr & 0x80000000)) {
+                               NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
+                                            "subc %d class 0x%04x mthd 0x%04x "
+                                            "data 0x%08x 40084c 0x%08x\n",
+                                       chid, inst, subc, class, mthd,
+                                       data, addr);
+                       } else
+                       if (display) {
+                               NV_INFO(dev, "PGRAPH - no stuck command?\n");
+                       }
+
+                       nv_wr32(dev, 0x40084c, 0);
+                       ustatus &= ~0x00000002;
+               }
+
+               if (ustatus && display) {
+                       NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
+                                     "0x%08x)\n", ustatus);
+               }
+
+               nv_wr32(dev, 0x400804, 0xc0000000);
+               nv_wr32(dev, 0x400108, 0x001);
+               status &= ~0x001;
+               if (!status)
+                       return 0;
+       }
+
+       /* M2MF: Memory to memory copy engine. */
+       if (status & 0x002) {
+               u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
+               if (display) {
+                       NV_INFO(dev, "PGRAPH - TRAP_M2MF");
+                       nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
+                               nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
+                               nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
+
+               }
+
+               /* No sane way found yet -- just reset the bugger. */
+               nv_wr32(dev, 0x400040, 2);
+               nv_wr32(dev, 0x400040, 0);
+               nv_wr32(dev, 0x406800, 0xc0000000);
+               nv_wr32(dev, 0x400108, 0x002);
+               status &= ~0x002;
+       }
+
+       /* VFETCH: Fetches data from vertex buffers. */
+       if (status & 0x004) {
+               u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
+               if (display) {
+                       NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
+                       nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
+                               nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
+                               nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
+               }
+
+               nv_wr32(dev, 0x400c04, 0xc0000000);
+               nv_wr32(dev, 0x400108, 0x004);
+               status &= ~0x004;
+       }
+
+       /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
+       if (status & 0x008) {
+               ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
+               if (display) {
+                       NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
+                       nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
+                               nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
+                               nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
+
+               }
+
+               /* No sane way found yet -- just reset the bugger. */
+               nv_wr32(dev, 0x400040, 0x80);
+               nv_wr32(dev, 0x400040, 0);
+               nv_wr32(dev, 0x401800, 0xc0000000);
+               nv_wr32(dev, 0x400108, 0x008);
+               status &= ~0x008;
+       }
+
+       /* CCACHE: Handles code and c[] caches and fills them. */
+       if (status & 0x010) {
+               ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
+               if (display) {
+                       NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
+                       nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
+                                    " %08x %08x %08x\n",
+                               nv_rd32(dev, 0x405800), nv_rd32(dev, 0x405804),
+                               nv_rd32(dev, 0x405808), nv_rd32(dev, 0x40580c),
+                               nv_rd32(dev, 0x405810), nv_rd32(dev, 0x405814),
+                               nv_rd32(dev, 0x40581c));
+
+               }
+
+               nv_wr32(dev, 0x405018, 0xc0000000);
+               nv_wr32(dev, 0x400108, 0x010);
+               status &= ~0x010;
+       }
+
+       /* Unknown, not seen yet... 0x402000 is the only trap status reg
+        * remaining, so try to handle it anyway. Perhaps related to that
+        * unknown DMA slot on tesla? */
+       if (status & 0x20) {
+               ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
+               if (display)
+                       NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
+               nv_wr32(dev, 0x402000, 0xc0000000);
+               /* no status modifiction on purpose */
+       }
+
+       /* TEXTURE: CUDA texturing units */
+       if (status & 0x040) {
+               nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
+                                   "PGRAPH - TRAP_TEXTURE");
+               nv_wr32(dev, 0x400108, 0x040);
+               status &= ~0x040;
+       }
+
+       /* MP: CUDA execution engines. */
+       if (status & 0x080) {
+               nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
+                                   "PGRAPH - TRAP_MP");
+               nv_wr32(dev, 0x400108, 0x080);
+               status &= ~0x080;
+       }
+
+       /* TPDMA:  Handles TP-initiated uncached memory accesses:
+        * l[], g[], stack, 2d surfaces, render targets. */
+       if (status & 0x100) {
+               nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
+                                   "PGRAPH - TRAP_TPDMA");
+               nv_wr32(dev, 0x400108, 0x100);
+               status &= ~0x100;
+       }
+
+       if (status) {
+               if (display)
+                       NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
+               nv_wr32(dev, 0x400108, status);
+       }
+
+       return 1;
+}
+
+static int
+nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
+{
+       struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_channel *chan;
+       unsigned long flags;
+       int i;
+
+       spin_lock_irqsave(&dev_priv->channels.lock, flags);
+       for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
+               chan = dev_priv->channels.ptr[i];
+               if (!chan || !chan->ramin)
+                       continue;
+
+               if (inst == chan->ramin->vinst)
+                       break;
+       }
+       spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+       return i;
+}
+
+static void
+nv50_graph_isr(struct drm_device *dev)
+{
+       u32 stat;
+
+       while ((stat = nv_rd32(dev, 0x400100))) {
+               u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
+               u32 chid = nv50_graph_isr_chid(dev, inst);
+               u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
+               u32 subc = (addr & 0x00070000) >> 16;
+               u32 mthd = (addr & 0x00001ffc);
+               u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
+               u32 class = nv_rd32(dev, 0x400814);
+               u32 show = stat;
+
+               if (stat & 0x00000010) {
+                       if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
+                                                      mthd, data))
+                               show &= ~0x00000010;
+               }
+
+               if (stat & 0x00001000) {
+                       nv_wr32(dev, 0x400500, 0x00000000);
+                       nv_wr32(dev, 0x400100, 0x00001000);
+                       nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
+                       nv50_graph_context_switch(dev);
+                       stat &= ~0x00001000;
+                       show &= ~0x00001000;
+               }
+
+               show = (show && nouveau_ratelimit()) ? show : 0;
+
+               if (show & 0x00100000) {
+                       u32 ecode = nv_rd32(dev, 0x400110);
+                       NV_INFO(dev, "PGRAPH - DATA_ERROR ");
+                       nouveau_enum_print(nv50_data_error_names, ecode);
+                       printk("\n");
+               }
+
+               if (stat & 0x00200000) {
+                       if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
+                               show &= ~0x00200000;
+               }
+
+               nv_wr32(dev, 0x400100, stat);
+               nv_wr32(dev, 0x400500, 0x00010001);
+
+               if (show) {
+                       NV_INFO(dev, "PGRAPH -");
+                       nouveau_bitfield_print(nv50_graph_intr, show);
+                       printk("\n");
+                       NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
+                                    "class 0x%04x mthd 0x%04x data 0x%08x\n",
+                               chid, inst, subc, class, mthd, data);
+               }
+       }
+
+       if (nv_rd32(dev, 0x400824) & (1 << 31))
+               nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
+}