continue;
/* skip overclock modes for now */
if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
- rdev->clock.default_mclk) ||
+ rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
(rdev->pm.power_state[state_index].clock_info[0].sclk >
- rdev->clock.default_sclk))
+ rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
continue;
rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
continue;
/* skip overclock modes for now */
if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
- rdev->clock.default_mclk) ||
+ rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
(rdev->pm.power_state[state_index].clock_info[0].sclk >
- rdev->clock.default_sclk))
+ rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
continue;
rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
continue;
/* skip overclock modes for now */
if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
- rdev->clock.default_mclk) ||
+ rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
(rdev->pm.power_state[state_index].clock_info[0].sclk >
- rdev->clock.default_sclk))
+ rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
continue;
rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
continue;
/* skip overclock modes for now */
if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
- rdev->clock.default_sclk)
+ rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
continue;
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
VOLTAGE_SW;
continue;
/* skip overclock modes for now */
if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
- rdev->clock.default_mclk) ||
+ rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
(rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
- rdev->clock.default_sclk))
+ rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
continue;
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
VOLTAGE_SW;
goto default_mode;
/* skip overclock modes for now */
if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
- rdev->clock.default_mclk) ||
+ rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
(rdev->pm.power_state[state_index].clock_info[0].sclk >
- rdev->clock.default_sclk))
+ rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
goto default_mode;
rdev->pm.power_state[state_index].type =
POWER_STATE_TYPE_BATTERY;