drm: Nuke fb->bits_per_pixel

Replace uses of fb->bits_per_pixel with fb->format->cpp[0]*8.
Less duplicated information is a good thing.

Note that I didn't put parens around the cpp*8 in the below cocci script,
on account of not wanting spurious parens all over the place. Instead I
did the unsafe way, and tried to look over the entire diff to spot if
any dangerous expressions were produced. I didn't see any.

There are some cases where previously the code did X*bpp/8, so the
division happened after the multiplication. Those are now just X*cpp
so the division effectively happens before the multiplication,
but that is perfectly fine since bpp is always a multiple of 8.

@@
struct drm_framebuffer *FB;
expression E;
@@
 drm_helper_mode_fill_fb_struct(...) {
	...
-	FB->bits_per_pixel = E;
	...
 }

@@
struct drm_framebuffer *FB;
expression E;
@@
 i9xx_get_initial_plane_config(...) {
	...
-	FB->bits_per_pixel = E;
	...
 }

@@
struct drm_framebuffer *FB;
expression E;
@@
 ironlake_get_initial_plane_config(...) {
	...
-	FB->bits_per_pixel = E;
	...
 }

@@
struct drm_framebuffer *FB;
expression E;
@@
 skylake_get_initial_plane_config(...) {
	...
-	FB->bits_per_pixel = E;
	...
 }

@@
struct drm_framebuffer FB;
expression E;
@@
(
- E * FB.bits_per_pixel / 8
+ E * FB.format->cpp[0]
|
- FB.bits_per_pixel / 8
+ FB.format->cpp[0]
|
- E * FB.bits_per_pixel >> 3
+ E * FB.format->cpp[0]
|
- FB.bits_per_pixel >> 3
+ FB.format->cpp[0]
|
- (FB.bits_per_pixel + 7) / 8
+ FB.format->cpp[0]
|
- FB.bits_per_pixel
+ FB.format->cpp[0] * 8
|
- FB.format->cpp[0] * 8 != 8
+ FB.format->cpp[0] != 1
)

@@
struct drm_framebuffer *FB;
expression E;
@@
(
- E * FB->bits_per_pixel / 8
+ E * FB->format->cpp[0]
|
- FB->bits_per_pixel / 8
+ FB->format->cpp[0]
|
- E * FB->bits_per_pixel >> 3
+ E * FB->format->cpp[0]
|
- FB->bits_per_pixel >> 3
+ FB->format->cpp[0]
|
- (FB->bits_per_pixel + 7) / 8
+ FB->format->cpp[0]
|
- FB->bits_per_pixel
+ FB->format->cpp[0] * 8
|
- FB->format->cpp[0] * 8 != 8
+ FB->format->cpp[0] != 1
)

@@
struct drm_plane_state *state;
expression E;
@@
(
- E * state->fb->bits_per_pixel / 8
+ E * state->fb->format->cpp[0]
|
- state->fb->bits_per_pixel / 8
+ state->fb->format->cpp[0]
|
- E * state->fb->bits_per_pixel >> 3
+ E * state->fb->format->cpp[0]
|
- state->fb->bits_per_pixel >> 3
+ state->fb->format->cpp[0]
|
- (state->fb->bits_per_pixel + 7) / 8
+ state->fb->format->cpp[0]
|
- state->fb->bits_per_pixel
+ state->fb->format->cpp[0] * 8
|
- state->fb->format->cpp[0] * 8 != 8
+ state->fb->format->cpp[0] != 1
)

@@
@@
- (8 * 8)
+ 8 * 8

@@
struct drm_framebuffer FB;
@@
- (FB.format->cpp[0])
+ FB.format->cpp[0]

@@
struct drm_framebuffer *FB;
@@
- (FB->format->cpp[0])
+ FB->format->cpp[0]

@@
@@
 struct drm_framebuffer {
	 ...
-	 int bits_per_pixel;
	 ...
 };

v2: Clean up the 'cpp*8 != 8' and '(8 * 8)' cases (Laurent)
v3: Adjusted the semantic patch a bit and regenerated due to code
    changes

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1481751140-18352-1-git-send-email-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 9999dc71b998599f909464c32e98ca8cc1be5ddb..8d0ff1c8db8e0a5506fb2348295ff55a48c23e3b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2220,7 +2220,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
        WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
 
-       fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
+       fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
        WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
 
        dce_v10_0_grph_enable(crtc, true);

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index b3d62b909f4372db1e569308e29a436de873d0c9..c25edecb46d4db17d503566cdeca843d31eb1929 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2201,7 +2201,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
        WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
 
-       fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
+       fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
        WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
 
        dce_v11_0_grph_enable(crtc, true);

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index e564442b6393f82520aad6e2f47f99e23f7c68bc..ffd20f90788c6429290e8ad497de89bd7adf7703 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1630,7 +1630,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
        WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
 
-       fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
+       fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
        WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
 
        dce_v6_0_grph_enable(crtc, true);

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 6ce7fb42dbef68232a8325d720d54bf99b3c8783..e6f446af381814fd3b264aa254541fbc6e5a74c3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2079,7 +2079,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
        WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
 
-       fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
+       fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
        WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
 
        dce_v8_0_grph_enable(crtc, true);

diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 99283f30edc5d89081d37ec87f009c7da39a9ecc..426e86f4cf96fbeec164ce342f4d7be8976b1951 100644 (file)
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -190,7 +190,7 @@ static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
        unsigned i = 0;
 
        DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
-               pitch, x, y, fb->bits_per_pixel);
+               pitch, x, y, fb->format->cpp[0] * 8);
 
        armada_drm_plane_calc_addrs(addrs, fb, x, y);
 

diff --git a/drivers/gpu/drm/armada/armada_fbdev.c b/drivers/gpu/drm/armada/armada_fbdev.c
index 3a58fb600b052b83dd596c11c3611361ea3c4796..78335100cbc3e69f770d7ca1852ec7a83b6f1612 100644 (file)
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -94,7 +94,7 @@ static int armada_fb_create(struct drm_fb_helper *fbh,
        drm_fb_helper_fill_var(info, fbh, sizes->fb_width, sizes->fb_height);
 
        DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08llx\n",
-               dfb->fb.width, dfb->fb.height, dfb->fb.bits_per_pixel,
+               dfb->fb.width, dfb->fb.height, dfb->fb.format->cpp[0] * 8,
                (unsigned long long)obj->phys_addr);
 
        return 0;

diff --git a/drivers/gpu/drm/ast/ast_fb.c b/drivers/gpu/drm/ast/ast_fb.c
index f751792a3c7c448d9aaedd198e61212bcd83e143..b085140fae958fea9392435fa84aa2e7993a348d 100644 (file)
--- a/drivers/gpu/drm/ast/ast_fb.c
+++ b/drivers/gpu/drm/ast/ast_fb.c
@@ -49,7 +49,7 @@ static void ast_dirty_update(struct ast_fbdev *afbdev,
        struct drm_gem_object *obj;
        struct ast_bo *bo;
        int src_offset, dst_offset;
-       int bpp = (afbdev->afb.base.bits_per_pixel + 7)/8;
+       int bpp = afbdev->afb.base.format->cpp[0];
        int ret = -EBUSY;
        bool unmap = false;
        bool store_for_later = false;

diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
index e70364a8544ec0803cdab752befe20f94cb15c2e..606cb40f6c7cd6ccdaee2d5d1c61e7c105049689 100644 (file)
--- a/drivers/gpu/drm/ast/ast_mode.c
+++ b/drivers/gpu/drm/ast/ast_mode.c
@@ -85,7 +85,7 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
        bool check_sync;
        struct ast_vbios_enhtable *best = NULL;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
                color_index = VGAModeIndex - 1;
@@ -208,7 +208,8 @@ static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mo
                ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
                if (vbios_mode->enh_table->flags & NewModeInfo) {
                        ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
-                       ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, fb->bits_per_pixel);
+                       ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92,
+                                         fb->format->cpp[0] * 8);
                        ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
                        ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
                        ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
@@ -400,7 +401,7 @@ static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
        const struct drm_framebuffer *fb = crtc->primary->fb;
        u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                jregA0 = 0x70;
                jregA3 = 0x01;
@@ -457,7 +458,7 @@ static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode
 {
        const struct drm_framebuffer *fb = crtc->primary->fb;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                break;
        default:

diff --git a/drivers/gpu/drm/cirrus/cirrus_fbdev.c b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
index 3cac8a03cf4f2dd1344689924bc2b349703b7ecb..79a5cd10824530ba95e1b6219c837d106682aa5c 100644 (file)
--- a/drivers/gpu/drm/cirrus/cirrus_fbdev.c
+++ b/drivers/gpu/drm/cirrus/cirrus_fbdev.c
@@ -22,7 +22,7 @@ static void cirrus_dirty_update(struct cirrus_fbdev *afbdev,
        struct drm_gem_object *obj;
        struct cirrus_bo *bo;
        int src_offset, dst_offset;
-       int bpp = (afbdev->gfb.base.bits_per_pixel + 7)/8;
+       int bpp = afbdev->gfb.base.format->cpp[0];
        int ret = -EBUSY;
        bool unmap = false;
        bool store_for_later = false;

diff --git a/drivers/gpu/drm/cirrus/cirrus_mode.c b/drivers/gpu/drm/cirrus/cirrus_mode.c
index 06674a9b7665e471cba77139438c7cf0474228e5..ed43ab10ac993d16e7ce44767cbaa87522e1e1cc 100644 (file)
--- a/drivers/gpu/drm/cirrus/cirrus_mode.c
+++ b/drivers/gpu/drm/cirrus/cirrus_mode.c
@@ -258,7 +258,7 @@ static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
        sr07 = RREG8(SEQ_DATA);
        sr07 &= 0xe0;
        hdr = 0;
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                sr07 |= 0x11;
                break;

diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 96c78b33a99941ef38e6c1adc63906f18aa62bba..bee5e4149a1c9b2add71cf0e4d9963cfc22f7cd8 100644 (file)
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1169,7 +1169,7 @@ static int setcolreg(struct drm_crtc *crtc, u16 red, u16 green,
                    !fb_helper->funcs->gamma_get))
                return -EINVAL;
 
-       WARN_ON(fb->bits_per_pixel != 8);
+       WARN_ON(fb->format->cpp[0] != 1);
 
        fb_helper->funcs->gamma_set(crtc, red, green, blue, regno);
 
@@ -1252,14 +1252,14 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
         * Changes struct fb_var_screeninfo are currently not pushed back
         * to KMS, hence fail if different settings are requested.
         */
-       if (var->bits_per_pixel != fb->bits_per_pixel ||
+       if (var->bits_per_pixel != fb->format->cpp[0] * 8 ||
            var->xres != fb->width || var->yres != fb->height ||
            var->xres_virtual != fb->width || var->yres_virtual != fb->height) {
                DRM_DEBUG("fb userspace requested width/height/bpp different than current fb "
                          "request %dx%d-%d (virtual %dx%d) > %dx%d-%d\n",
                          var->xres, var->yres, var->bits_per_pixel,
                          var->xres_virtual, var->yres_virtual,
-                         fb->width, fb->height, fb->bits_per_pixel);
+                         fb->width, fb->height, fb->format->cpp[0] * 8);
                return -EINVAL;
        }
 
@@ -1645,7 +1645,7 @@ void drm_fb_helper_fill_var(struct fb_info *info, struct drm_fb_helper *fb_helpe
        info->pseudo_palette = fb_helper->pseudo_palette;
        info->var.xres_virtual = fb->width;
        info->var.yres_virtual = fb->height;
-       info->var.bits_per_pixel = fb->bits_per_pixel;
+       info->var.bits_per_pixel = fb->format->cpp[0] * 8;
        info->var.accel_flags = FB_ACCELF_TEXT;
        info->var.xoffset = 0;
        info->var.yoffset = 0;

diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c
index 556a92359c961417bf9022e9d2d0e34c2139cc39..94ddab41f24f3f01c80f6cd9da1a00534426f92d 100644 (file)
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -433,7 +433,7 @@ int drm_mode_getfb(struct drm_device *dev,
        r->height = fb->height;
        r->width = fb->width;
        r->depth = fb->format->depth;
-       r->bpp = fb->bits_per_pixel;
+       r->bpp = fb->format->cpp[0] * 8;
        r->pitch = fb->pitches[0];
        if (fb->funcs->create_handle) {
                if (drm_is_current_master(file_priv) || capable(CAP_SYS_ADMIN) ||

diff --git a/drivers/gpu/drm/drm_modeset_helper.c b/drivers/gpu/drm/drm_modeset_helper.c
index e5d19e5fc341f3e8435b1f08f4cadf2eec3a2211..3c44409244dc51ad779165ecd4281ca9ab2ad584 100644 (file)
--- a/drivers/gpu/drm/drm_modeset_helper.c
+++ b/drivers/gpu/drm/drm_modeset_helper.c
@@ -82,10 +82,7 @@ void drm_helper_mode_fill_fb_struct(struct drm_device *dev,
                DRM_DEBUG_KMS("non-RGB pixel format %s\n",
                              drm_get_format_name(mode_cmd->pixel_format,
                                                  &format_name));
-
-               fb->bits_per_pixel = 0;
        } else {
-               fb->bits_per_pixel = info->cpp[0] * 8;
        }
 
        fb->dev = dev;

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 6ca1f3117fe8d524fbb4dfed89692c527c5bd41c..e8ce4a31858678aad4f9851d2ba485f9894a7afc 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -226,7 +226,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
                return;
        }
 
-       DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
+       DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 
        /*
         * In case of exynos, setting dma-burst to 16Word causes permanent
@@ -275,7 +275,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
        struct decon_context *ctx = crtc->ctx;
        struct drm_framebuffer *fb = state->base.fb;
        unsigned int win = plane->index;
-       unsigned int bpp = fb->bits_per_pixel >> 3;
+       unsigned int bpp = fb->format->cpp[0];
        unsigned int pitch = fb->pitches[0];
        dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
        u32 val;

diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index f4d5a2133777d8cd40df1d7a346c301cf7c5313c..58dc9a5196bcaece92fe5b83bc30e1355bbb25cd 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -330,7 +330,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
                break;
        }
 
-       DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
+       DRM_DEBUG_KMS("bpp = %d\n", fb->format->cpp[0] * 8);
 
        /*
         * In case of exynos, setting dma-burst to 16Word causes permanent
@@ -340,7 +340,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
         * movement causes unstable DMA which results into iommu crash/tear.
         */
 
-       padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
+       padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
        if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
                val &= ~WINCONx_BURSTLEN_MASK;
                val |= WINCONx_BURSTLEN_8WORD;
@@ -407,7 +407,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
        unsigned int last_x;
        unsigned int last_y;
        unsigned int win = plane->index;
-       unsigned int bpp = fb->bits_per_pixel >> 3;
+       unsigned int bpp = fb->format->cpp[0];
        unsigned int pitch = fb->pitches[0];
 
        if (ctx->suspended)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index e68a46f112f6f7b6354d4ead214a040f9a5285d8..d8808158d41807c1b40802d1d9ee72d8f6822f5e 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -76,7 +76,7 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper,
 {
        struct fb_info *fbi;
        struct drm_framebuffer *fb = helper->fb;
-       unsigned int size = fb->width * fb->height * (fb->bits_per_pixel >> 3);
+       unsigned int size = fb->width * fb->height * fb->format->cpp[0];
        unsigned int nr_pages;
        unsigned long offset;
 
@@ -103,7 +103,7 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper,
                return -EIO;
        }
 
-       offset = fbi->var.xoffset * (fb->bits_per_pixel >> 3);
+       offset = fbi->var.xoffset * fb->format->cpp[0];
        offset += fbi->var.yoffset * fb->pitches[0];
 
        fbi->screen_base = exynos_gem->kvaddr + offset;

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index e2e405170d35762a209ae9cb13d58fde87e310e7..0029065979b8b2531accaafb7de5e4037558a35f 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -738,7 +738,7 @@ static void fimd_update_plane(struct exynos_drm_crtc *crtc,
        unsigned long val, size, offset;
        unsigned int last_x, last_y, buf_offsize, line_size;
        unsigned int win = plane->index;
-       unsigned int bpp = fb->bits_per_pixel >> 3;
+       unsigned int bpp = fb->format->cpp[0];
        unsigned int pitch = fb->pitches[0];
 
        if (ctx->suspended)

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index edb20a34c66c06f1533513f02ed9eaceedeed63b..b313e61aab6549850ba0e32c4c5625cfe68e697c 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -631,7 +631,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
 
        /* converting dma address base and source offset */
        dma_addr = exynos_drm_fb_dma_addr(fb, 0)
-               + (state->src.x * fb->bits_per_pixel >> 3)
+               + (state->src.x * fb->format->cpp[0])
                + (state->src.y * fb->pitches[0]);
        src_x_offset = 0;
        src_y_offset = 0;
@@ -649,7 +649,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
 
        /* setup geometry */
        mixer_reg_write(res, MXR_GRAPHIC_SPAN(win),
-                       fb->pitches[0] / (fb->bits_per_pixel >> 3));
+                       fb->pitches[0] / fb->format->cpp[0]);
 
        /* setup display size */
        if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&

diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index a93b59ce6b41f2ff38d5293657afdf3d4fcee3c5..6bf33ba055b39c1f31350a4feda8a30315ff49a1 100644 (file)
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -77,7 +77,7 @@ static int psbfb_setcolreg(unsigned regno, unsigned red, unsigned green,
            (transp << info->var.transp.offset);
 
        if (regno < 16) {
-               switch (fb->bits_per_pixel) {
+               switch (fb->format->cpp[0] * 8) {
                case 16:
                        ((uint32_t *) info->pseudo_palette)[regno] = v;
                        break;

diff --git a/drivers/gpu/drm/gma500/gma_display.c b/drivers/gpu/drm/gma500/gma_display.c
index 5b852ad152ae791e8e827cd4674b9cf51bda0c09..d1c5642b1c1e3d3bc21d48f025af3083aac80d7b 100644 (file)
--- a/drivers/gpu/drm/gma500/gma_display.c
+++ b/drivers/gpu/drm/gma500/gma_display.c
@@ -82,14 +82,14 @@ int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
        if (ret < 0)
                goto gma_pipe_set_base_exit;
        start = psbfb->gtt->offset;
-       offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+       offset = y * fb->pitches[0] + x * fb->format->cpp[0];
 
        REG_WRITE(map->stride, fb->pitches[0]);
 
        dspcntr = REG_READ(map->cntr);
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                dspcntr |= DISPPLANE_8BPP;
                break;

diff --git a/drivers/gpu/drm/gma500/mdfld_intel_display.c b/drivers/gpu/drm/gma500/mdfld_intel_display.c
index 3be3111825cd9e2a3abbd58540425ee76f14eecf..63c6e08600ae3a2351993dd5b6b824102a1e5420 100644 (file)
--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
+++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
@@ -148,7 +148,7 @@ static int check_fb(struct drm_framebuffer *fb)
        if (!fb)
                return 0;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
        case 16:
        case 24:
@@ -197,13 +197,13 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                return 0;
 
        start = psbfb->gtt->offset;
-       offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+       offset = y * fb->pitches[0] + x * fb->format->cpp[0];
 
        REG_WRITE(map->stride, fb->pitches[0]);
        dspcntr = REG_READ(map->cntr);
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                dspcntr |= DISPPLANE_8BPP;
                break;

diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c
index 569810d47786b611880a2ef0706ed60767fd6a9c..0fff269d3fe68ee3e036cbda37fdfd1e63b2a984 100644 (file)
--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
+++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
@@ -618,14 +618,14 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
                return 0;
 
        start = psbfb->gtt->offset;
-       offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
+       offset = y * fb->pitches[0] + x * fb->format->cpp[0];
 
        REG_WRITE(map->stride, fb->pitches[0]);
 
        dspcntr = REG_READ(map->cntr);
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                dspcntr |= DISPPLANE_8BPP;
                break;

diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
index 2a1386e3312642ee9ce4f9d31a87f6295716fa1e..c655883d3613c63c81e100ec32d878f36c499dcc 100644 (file)
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
@@ -122,11 +122,11 @@ static void hibmc_plane_atomic_update(struct drm_plane *plane,
 
        writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
 
-       reg = state->fb->width * (state->fb->bits_per_pixel / 8);
+       reg = state->fb->width * (state->fb->format->cpp[0]);
        /* now line_pad is 16 */
        reg = PADDING(16, reg);
 
-       line_l = state->fb->width * state->fb->bits_per_pixel / 8;
+       line_l = state->fb->width * state->fb->format->cpp[0];
        line_l = PADDING(16, line_l);
        writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |
               HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),
@@ -136,7 +136,7 @@ static void hibmc_plane_atomic_update(struct drm_plane *plane,
        reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);
        reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK;
        reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,
-                          state->fb->bits_per_pixel / 16);
+                          state->fb->format->cpp[0] * 8 / 16);
        writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);
 }
 

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ce5586451633565d3dff11cc2bfda4c4277a466a..ec462dae46bca026d88347823864557a3c6fc00e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1874,7 +1874,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
                           fbdev_fb->base.width,
                           fbdev_fb->base.height,
                           fbdev_fb->base.format->depth,
-                          fbdev_fb->base.bits_per_pixel,
+                          fbdev_fb->base.format->cpp[0] * 8,
                           fbdev_fb->base.modifier,
                           drm_framebuffer_read_refcount(&fbdev_fb->base));
                describe_obj(m, fbdev_fb->obj);
@@ -1892,7 +1892,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
                           fb->base.width,
                           fb->base.height,
                           fb->base.format->depth,
-                          fb->base.bits_per_pixel,
+                          fb->base.format->cpp[0] * 8,
                           fb->base.modifier,
                           drm_framebuffer_read_refcount(&fb->base));
                describe_obj(m, fb->obj);

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87a0bba764c73bd26ee5c6f4218a01dcd176a30f..4f0675460336934274935e16921177aa0d466409 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8715,7 +8715,6 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
        pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
        fourcc = i9xx_format_to_fourcc(pixel_format);
        fb->pixel_format = fourcc;
-       fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
        fb->format = drm_format_info(fourcc);
 
        if (INTEL_GEN(dev_priv) >= 4) {
@@ -8744,7 +8743,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
        DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
                      pipe_name(pipe), plane, fb->width, fb->height,
-                     fb->bits_per_pixel, base, fb->pitches[0],
+                     fb->format->cpp[0] * 8, base, fb->pitches[0],
                      plane_config->size);
 
        plane_config->fb = intel_fb;
@@ -9747,7 +9746,6 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
                                      val & PLANE_CTL_ORDER_RGBX,
                                      val & PLANE_CTL_ALPHA_MASK);
        fb->pixel_format = fourcc;
-       fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
        fb->format = drm_format_info(fourcc);
 
        tiling = val & PLANE_CTL_TILED_MASK;
@@ -9792,7 +9790,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
        DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
                      pipe_name(pipe), fb->width, fb->height,
-                     fb->bits_per_pixel, base, fb->pitches[0],
+                     fb->format->cpp[0] * 8, base, fb->pitches[0],
                      plane_config->size);
 
        plane_config->fb = intel_fb;
@@ -9863,7 +9861,6 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
        pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
        fourcc = i9xx_format_to_fourcc(pixel_format);
        fb->pixel_format = fourcc;
-       fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
        fb->format = drm_format_info(fourcc);
 
        base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
@@ -9892,7 +9889,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
        DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
                      pipe_name(pipe), fb->width, fb->height,
-                     fb->bits_per_pixel, base, fb->pitches[0],
+                     fb->format->cpp[0] * 8, base, fb->pitches[0],
                      plane_config->size);
 
        plane_config->fb = intel_fb;
@@ -11051,7 +11048,7 @@ mode_fits_in_fbdev(struct drm_device *dev,
 
        fb = &dev_priv->fbdev->fb->base;
        if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
-                                                              fb->bits_per_pixel))
+                                                              fb->format->cpp[0] * 8))
                return NULL;
 
        if (obj->base.size < mode->vdisplay * fb->pitches[0])

diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b726483a460ddcda2cc137ff707f1c3fd69b44f4..3f60a4f6f078b3f830a8900fc793d95cb3404f18 100644 (file)
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -621,7 +621,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
                 * rather than the current pipe's, since they differ.
                 */
                cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;
-               cur_size = cur_size * fb->base.bits_per_pixel / 8;
+               cur_size = cur_size * fb->base.format->cpp[0];
                if (fb->base.pitches[0] < cur_size) {
                        DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
                                      pipe_name(intel_crtc->pipe),
@@ -639,7 +639,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
                              pipe_name(intel_crtc->pipe),
                              intel_crtc->config->base.adjusted_mode.crtc_hdisplay,
                              intel_crtc->config->base.adjusted_mode.crtc_vdisplay,
-                             fb->base.bits_per_pixel,
+                             fb->base.format->cpp[0] * 8,
                              cur_size);
 
                if (cur_size > max_size) {
@@ -660,7 +660,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
                goto out;
        }
 
-       ifbdev->preferred_bpp = fb->base.bits_per_pixel;
+       ifbdev->preferred_bpp = fb->base.format->cpp[0] * 8;
        ifbdev->fb = fb;
 
        drm_framebuffer_reference(&ifbdev->fb->base);

diff --git a/drivers/gpu/drm/mgag200/mgag200_fb.c b/drivers/gpu/drm/mgag200/mgag200_fb.c
index 19a78b6b5a1a5b5883b0167bcd48aa62122c2634..1a665e1671b8fe657b06fe350af672815ce7aa9d 100644 (file)
--- a/drivers/gpu/drm/mgag200/mgag200_fb.c
+++ b/drivers/gpu/drm/mgag200/mgag200_fb.c
@@ -24,7 +24,7 @@ static void mga_dirty_update(struct mga_fbdev *mfbdev,
        struct drm_gem_object *obj;
        struct mgag200_bo *bo;
        int src_offset, dst_offset;
-       int bpp = (mfbdev->mfb.base.bits_per_pixel + 7)/8;
+       int bpp = mfbdev->mfb.base.format->cpp[0];
        int ret = -EBUSY;
        bool unmap = false;
        bool store_for_later = false;

diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 9399099d3e39967ff05027e17b353b4b5cd55ef1..067dfbc91b1c179288254579b7f00ff8509b8c41 100644 (file)
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -38,7 +38,7 @@ static void mga_crtc_load_lut(struct drm_crtc *crtc)
 
        WREG8(DAC_INDEX + MGA1064_INDEX, 0);
 
-       if (fb && fb->bits_per_pixel == 16) {
+       if (fb && fb->format->cpp[0] * 8 == 16) {
                int inc = (fb->format->depth == 15) ? 8 : 4;
                u8 r, b;
                for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
@@ -903,7 +903,7 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
                /* 0x48: */        0,    0,    0,    0,    0,    0,    0,    0
        };
 
-       bppshift = mdev->bpp_shifts[(fb->bits_per_pixel >> 3) - 1];
+       bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1];
 
        switch (mdev->type) {
        case G200_SE_A:
@@ -942,7 +942,7 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
                break;
        }
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
                break;
@@ -998,8 +998,8 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
        WREG_SEQ(3, 0);
        WREG_SEQ(4, 0xe);
 
-       pitch = fb->pitches[0] / (fb->bits_per_pixel / 8);
-       if (fb->bits_per_pixel == 24)
+       pitch = fb->pitches[0] / fb->format->cpp[0];
+       if (fb->format->cpp[0] * 8 == 24)
                pitch = (pitch * 3) >> (4 - bppshift);
        else
                pitch = pitch >> (4 - bppshift);
@@ -1076,7 +1076,7 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
                ((vdisplay & 0xc00) >> 7) |
                ((vsyncstart & 0xc00) >> 5) |
                ((vdisplay & 0x400) >> 3);
-       if (fb->bits_per_pixel == 24)
+       if (fb->format->cpp[0] * 8 == 24)
                ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
        else
                ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
@@ -1139,9 +1139,9 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
                        u32 bpp;
                        u32 mb;
 
-                       if (fb->bits_per_pixel > 16)
+                       if (fb->format->cpp[0] * 8 > 16)
                                bpp = 32;
-                       else if (fb->bits_per_pixel > 8)
+                       else if (fb->format->cpp[0] * 8 > 8)
                                bpp = 16;
                        else
                                bpp = 8;

diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 480e3ab477fd0cdde20ea13936e911f7f041540b..a72754d73c8462aa7fe232b26b037ab1d74a7d84 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -874,11 +874,11 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
 
        /* Update the framebuffer location. */
        regp->fb_start = nv_crtc->fb.offset & ~3;
-       regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
+       regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]);
        nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
 
        /* Update the arbitration parameters. */
-       nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
+       nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
                         &arb_burst, &arb_lwm);
 
        regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;

diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index e0db5d38fb18888888d5b18de7834a9fb2a9de53..c5cf88859b0b0f23e5b2eeb1c12128dd1a21d0ad 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -947,7 +947,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 
        /* Initialize a page flip struct */
        *s = (struct nouveau_page_flip_state)
-               { { }, event, crtc, fb->bits_per_pixel, fb->pitches[0],
+               { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0],
                  new_bo->bo.offset };
 
        /* Keep vblanks on during flip, for the target crtc of this flip */

diff --git a/drivers/gpu/drm/qxl/qxl_draw.c b/drivers/gpu/drm/qxl/qxl_draw.c
index 9b728edf1b49453b0a2e70bd06260822ae820525..4d8681e84e684f58fa5aec6e1da3c44818befb0e 100644 (file)
--- a/drivers/gpu/drm/qxl/qxl_draw.c
+++ b/drivers/gpu/drm/qxl/qxl_draw.c
@@ -283,7 +283,7 @@ void qxl_draw_dirty_fb(struct qxl_device *qdev,
        struct qxl_rect *rects;
        int stride = qxl_fb->base.pitches[0];
        /* depth is not actually interesting, we don't mask with it */
-       int depth = qxl_fb->base.bits_per_pixel;
+       int depth = qxl_fb->base.format->cpp[0] * 8;
        uint8_t *surface_base;
        struct qxl_release *release;
        struct qxl_bo *clips_bo;

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 05f4ebe31ce2d6c46a4219d0c0725443443cfe95..0d7f84f7d71d774355931850d913ab39515aa275 100644 (file)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1277,7 +1277,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 
                                /* Calculate the macrotile mode index. */
                                tile_split_bytes = 64 << tile_split;
-                               tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
+                               tileb = 8 * 8 * target_fb->format->cpp[0];
                                tileb = min(tile_split_bytes, tileb);
 
                                for (index = 0; tileb > 64; index++)
@@ -1285,13 +1285,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 
                                if (index >= 16) {
                                        DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
-                                                 target_fb->bits_per_pixel, tile_split);
+                                                 target_fb->format->cpp[0] * 8,
+                                                 tile_split);
                                        return -EINVAL;
                                }
 
                                num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
                        } else {
-                               switch (target_fb->bits_per_pixel) {
+                               switch (target_fb->format->cpp[0] * 8) {
                                case 8:
                                        index = 10;
                                        break;
@@ -1414,7 +1415,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
        WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
 
-       fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
+       fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
        WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
        WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 
@@ -1621,7 +1622,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
        WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
        WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
 
-       fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
+       fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
        WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
        WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 984b35f43554e9bd24ef6b8cd613fbbd46033583..e3399310d41dc1c8cb40229e13a78aad5759d50a 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3229,7 +3229,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
                        rdev->mode_info.crtcs[0]->base.primary->fb;
 
                mode1 = &rdev->mode_info.crtcs[0]->base.mode;
-               pixel_bytes1 = fb->bits_per_pixel / 8;
+               pixel_bytes1 = fb->format->cpp[0];
        }
        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
                if (rdev->mode_info.crtcs[1]->base.enabled) {
@@ -3237,7 +3237,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
                                rdev->mode_info.crtcs[1]->base.primary->fb;
 
                        mode2 = &rdev->mode_info.crtcs[1]->base.mode;
-                       pixel_bytes2 = fb->bits_per_pixel / 8;
+                       pixel_bytes2 = fb->format->cpp[0];
                }
        }
 

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 6285355eb5d562d7b9d5167929eb17bff4599f13..aea8b62835a4ad91b23d906c267e3c7b12432033 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -549,19 +549,19 @@ static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
        if (!ASIC_IS_AVIVO(rdev)) {
                /* crtc offset is from display base addr not FB location */
                base -= radeon_crtc->legacy_display_base_addr;
-               pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
+               pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
 
                if (tiling_flags & RADEON_TILING_MACRO) {
                        if (ASIC_IS_R300(rdev)) {
                                base &= ~0x7ff;
                        } else {
-                               int byteshift = fb->bits_per_pixel >> 4;
+                               int byteshift = fb->format->cpp[0] * 8 >> 4;
                                int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
                                base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
                        }
                } else {
                        int offset = crtc->y * pitch_pixels + crtc->x;
-                       switch (fb->bits_per_pixel) {
+                       switch (fb->format->cpp[0] * 8) {
                        case 8:
                        default:
                                offset *= 1;

diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 31c03e32a6b5c068620851f8c1171290faa3ff1f..ce6cb66662127aade60da663e38aedb5fddf3824 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -402,7 +402,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
                target_fb = crtc->primary->fb;
        }
 
-       switch (target_fb->bits_per_pixel) {
+       switch (target_fb->format->cpp[0] * 8) {
        case 8:
                format = 2;
                break;
@@ -476,9 +476,9 @@ retry:
 
        crtc_offset_cntl = 0;
 
-       pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
-       crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->bits_per_pixel,
-                                 target_fb->bits_per_pixel * 8);
+       pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
+       crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8,
+                                 target_fb->format->cpp[0] * 8 * 8);
        crtc_pitch |= crtc_pitch << 16;
 
        crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
@@ -503,14 +503,14 @@ retry:
                        crtc_tile_x0_y0 = x | (y << 16);
                        base &= ~0x7ff;
                } else {
-                       int byteshift = target_fb->bits_per_pixel >> 4;
+                       int byteshift = target_fb->format->cpp[0] * 8 >> 4;
                        int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
                        base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
                        crtc_offset_cntl |= (y % 16);
                }
        } else {
                int offset = y * pitch_pixels + x;
-               switch (target_fb->bits_per_pixel) {
+               switch (target_fb->format->cpp[0] * 8) {
                case 8:
                        offset *= 1;
                        break;
@@ -602,7 +602,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
                }
        }
 
-       switch (fb->bits_per_pixel) {
+       switch (fb->format->cpp[0] * 8) {
        case 8:
                format = 2;
                break;

diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index b60c306190e972d1113f5d084a0c4970bce847fa..642dcff87e34e721bb267fe579ec8d30e42ae473 100644 (file)
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -568,7 +568,7 @@ static void tegra_plane_atomic_update(struct drm_plane *plane,
        window.dst.y = plane->state->crtc_y;
        window.dst.w = plane->state->crtc_w;
        window.dst.h = plane->state->crtc_h;
-       window.bits_per_pixel = fb->bits_per_pixel;
+       window.bits_per_pixel = fb->format->cpp[0] * 8;
        window.bottom_up = tegra_fb_is_bottom_up(fb);
 
        /* copy from state */

diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index d2893f65341a7253f7a27dffc04d48455e71e12f..e289dbc6ad82d4fbb0424e7d97146b7011ec6d47 100644 (file)
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -877,7 +877,7 @@ static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
                seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
                           fb->base.id, fb->width, fb->height,
                           fb->format->depth,
-                          fb->bits_per_pixel,
+                          fb->format->cpp[0] * 8,
                           drm_framebuffer_read_refcount(fb));
        }
 

diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
index e21a3ed3ab2b4853dcab6b96cc7422f414f35bdd..b8dc06d68777973c3a7ec11a57af5ca86cf28567 100644 (file)
--- a/drivers/gpu/drm/udl/udl_fb.c
+++ b/drivers/gpu/drm/udl/udl_fb.c
@@ -89,7 +89,7 @@ int udl_handle_damage(struct udl_framebuffer *fb, int x, int y,
        int bytes_identical = 0;
        struct urb *urb;
        int aligned_x;
-       int bpp = (fb->base.bits_per_pixel / 8);
+       int bpp = fb->base.format->cpp[0];
 
        if (!fb->active_16)
                return 0;

diff --git a/drivers/gpu/drm/virtio/virtgpu_fb.c b/drivers/gpu/drm/virtio/virtgpu_fb.c
index 9d0da42cc42002d08d9a1fcbf1234d0b232dbc54..61254b991265e5af488eac6717ad87e3c04eb6e3 100644 (file)
--- a/drivers/gpu/drm/virtio/virtgpu_fb.c
+++ b/drivers/gpu/drm/virtio/virtgpu_fb.c
@@ -43,7 +43,7 @@ static int virtio_gpu_dirty_update(struct virtio_gpu_framebuffer *fb,
        struct drm_device *dev = fb->base.dev;
        struct virtio_gpu_device *vgdev = dev->dev_private;
        bool store_for_later = false;
-       int bpp = fb->base.bits_per_pixel / 8;
+       int bpp = fb->base.format->cpp[0];
        int x2, y2;
        unsigned long flags;
        struct virtio_gpu_object *obj = gem_to_virtio_gpu_obj(fb->obj);

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
index 4a7a7d2997ddd94fc08058d8f9e5c7acaa344b3c..58643c5ca1d7b3339d1a7a84ad43cad7b994fff7 100644 (file)
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c
@@ -93,7 +93,7 @@ static int vmw_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
        default:
                DRM_ERROR("Bad depth %u, bpp %u.\n",
                          par->set_fb->format->depth,
-                         par->set_fb->bits_per_pixel);
+                         par->set_fb->format->cpp[0] * 8);
                return 1;
        }
 
@@ -198,7 +198,7 @@ static void vmw_fb_dirty_flush(struct work_struct *work)
         * Handle panning when copying from vmalloc to framebuffer.
         * Clip dirty area to framebuffer.
         */
-       cpp = (cur_fb->bits_per_pixel + 7) / 8;
+       cpp = cur_fb->format->cpp[0];
        max_x = par->fb_x + cur_fb->width;
        max_y = par->fb_y + cur_fb->height;
 

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index a3a839a3d4419ae7e4fa5ff6fe0a033ca5e5d220..3806148e1bdb5e40985045cd1ecf4dfa1222f898 100644 (file)
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -97,7 +97,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
                fb = entry->base.crtc.primary->fb;
 
                return vmw_kms_write_svga(dev_priv, w, h, fb->pitches[0],
-                                         fb->bits_per_pixel,
+                                         fb->format->cpp[0] * 8,
                                          fb->format->depth);
        }
 
@@ -106,7 +106,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv)
                fb = entry->base.crtc.primary->fb;
 
                vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitches[0],
-                                  fb->bits_per_pixel, fb->format->depth);
+                                  fb->format->cpp[0] * 8, fb->format->depth);
        }
 
        /* Make sure we always show something. */

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index 38d7b8a2b78edb91250d1425d9c57eea567a32db..d4268efc37d262459a49917c588627a97ce8c8bc 100644 (file)
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -618,7 +618,7 @@ static int do_dmabuf_define_gmrfb(struct vmw_private *dev_priv,
        }
 
        cmd->header = SVGA_CMD_DEFINE_GMRFB;
-       cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
+       cmd->body.format.bitsPerPixel = framebuffer->base.format->cpp[0] * 8;
        cmd->body.format.colorDepth = depth;
        cmd->body.format.reserved = 0;
        cmd->body.bytesPerLine = framebuffer->base.pitches[0];

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 94ad8d2acf9a2106cafdc9349c4f1518d5d85503..b27cd18ee66a3fe0f01105954fb6f48f74d24043 100644 (file)
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -424,7 +424,7 @@ static int vmw_stdu_bind_fb(struct vmw_private *dev_priv,
                 */
                if (new_content_type == SEPARATE_DMA) {
 
-                       switch (new_fb->bits_per_pixel) {
+                       switch (new_fb->format->cpp[0] * 8) {
                        case 32:
                                content_srf.format = SVGA3D_X8R8G8B8;
                                break;

diff --git a/include/drm/drm_framebuffer.h b/include/drm/drm_framebuffer.h
index 0c14f0adf161863d0edb49764c20c6df1737060b..72b9b4898915a0a7435b2e438bd94b1ac1826d51 100644 (file)
--- a/include/drm/drm_framebuffer.h
+++ b/include/drm/drm_framebuffer.h
@@ -169,13 +169,6 @@ struct drm_framebuffer {
         * pixels.
         */
        unsigned int height;
-       /**
-        * @bits_per_pixel: Storage used bits per pixel for RGB formats. 0 for
-        * everything else. Legacy information derived from @pixel_format, it's
-        * suggested to use the DRM FOURCC codes and helper functions directly
-        * instead.
-        */
-       int bits_per_pixel;
        /**
         * @flags: Framebuffer flags like DRM_MODE_FB_INTERLACED or
         * DRM_MODE_FB_MODIFIERS.