drm/i915: flush plane control changes on ILK+ as well

After writing to the plane control reg we need to write to the surface
reg to trigger the double buffered register latch.  On previous
chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg
that triggers the double buffer latch.

v2: write DSPADDR too to cover pre-965 chipsets
v3: use flush_display_plane instead, that's what it's for
v4: send the right patch

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 502efc37b07415a2f020c2145f24d43ab3e88c4b..a7a7b672c4c23c6ac12a5db89014b7e7d6f9c52e 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1323,8 +1323,8 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
                                      enum plane plane)
 {
-       u32 reg = DSPADDR(plane);
-       I915_WRITE(reg, I915_READ(reg));
+       I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
+       I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
 }
 
 /**