ixgbe: Fill out PCIe speed and width enums with values
authorEmil Tantilov <emil.s.tantilov@intel.com>
Thu, 17 Feb 2011 11:34:53 +0000 (11:34 +0000)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Thu, 3 Mar 2011 11:10:01 +0000 (03:10 -0800)
This patch fills in the values for bus speed and width of the
ixgbe_bus_speed and ixgbe_bus_width enums.

Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ixgbe/ixgbe_type.h

index 5ede03c84a5eb9ecaf0b35c8da3779972b71c7bb..a737b131061946eef9e71d6ebea182f16a1f3e1b 100644 (file)
@@ -2333,25 +2333,25 @@ enum ixgbe_bus_type {
 /* PCI bus speeds */
 enum ixgbe_bus_speed {
        ixgbe_bus_speed_unknown = 0,
-       ixgbe_bus_speed_33,
-       ixgbe_bus_speed_66,
-       ixgbe_bus_speed_100,
-       ixgbe_bus_speed_120,
-       ixgbe_bus_speed_133,
-       ixgbe_bus_speed_2500,
-       ixgbe_bus_speed_5000,
+       ixgbe_bus_speed_33      = 33,
+       ixgbe_bus_speed_66      = 66,
+       ixgbe_bus_speed_100     = 100,
+       ixgbe_bus_speed_120     = 120,
+       ixgbe_bus_speed_133     = 133,
+       ixgbe_bus_speed_2500    = 2500,
+       ixgbe_bus_speed_5000    = 5000,
        ixgbe_bus_speed_reserved
 };
 
 /* PCI bus widths */
 enum ixgbe_bus_width {
        ixgbe_bus_width_unknown = 0,
-       ixgbe_bus_width_pcie_x1,
-       ixgbe_bus_width_pcie_x2,
+       ixgbe_bus_width_pcie_x1 = 1,
+       ixgbe_bus_width_pcie_x2 = 2,
        ixgbe_bus_width_pcie_x4 = 4,
        ixgbe_bus_width_pcie_x8 = 8,
-       ixgbe_bus_width_32,
-       ixgbe_bus_width_64,
+       ixgbe_bus_width_32      = 32,
+       ixgbe_bus_width_64      = 64,
        ixgbe_bus_width_reserved
 };