case IOV_SVAL(IOV_SDIOD_DRIVE):
dhd_sdiod_drive_strength = int_val;
- si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
+ si_sdiod_drive_strength_init(bus->sih,
dhd_sdiod_drive_strength);
break;
F2SYNC, bus->dataptr,
dlen, NULL, NULL, NULL);
sublen =
- (u16) pktfrombuf(osh, pfirst, 0, dlen,
+ (u16) pktfrombuf(pfirst, 0, dlen,
bus->dataptr);
if (sublen != dlen) {
DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
#endif /* DHD_DEBUG */
/* si_attach() will provide an SI handle and scan the backplane */
- bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
+ bus->sih = si_attach((uint) devid, regsva, DHD_BUS, sdh,
&bus->vars, &bus->varsz);
if (!(bus->sih)) {
DHD_ERROR(("%s: si_attach failed!\n", __func__));
goto fail;
}
- si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
+ si_sdiod_drive_strength_init(bus->sih, dhd_sdiod_drive_strength);
/* Get info on the ARM and SOCRAM cores... */
if (!DHD_NOPMU(bus)) {
if ((pi->sh->chip == BCM4716_CHIP_ID) ||
(pi->sh->chip == BCM47162_CHIP_ID)) {
- si_pmu_spuravoid(pi->sh->sih, pi->sh->osh, spuravoid);
+ si_pmu_spuravoid(pi->sh->sih, spuravoid);
} else {
wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
- si_pmu_spuravoid(pi->sh->sih, pi->sh->osh, spuravoid);
+ si_pmu_spuravoid(pi->sh->sih, spuravoid);
wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
}
struct sk_buff **pdu, int prec)
{
struct wlc_info *wlc;
- struct osl_info *osh;
struct sk_buff *p, *pkt[AMPDU_MAX_MPDU];
u8 tid, ndelim;
int err = 0;
u16 qlen;
wlc = ampdu->wlc;
- osh = wlc->osh;
p = *pdu;
ASSERT(p);
wlc->pub->unit, txs->phyerr);
if (WL_ERROR_ON()) {
- prpkt("txpkt (AMPDU)", wlc->osh, p);
+ prpkt("txpkt (AMPDU)", p);
wlc_print_txdesc((d11txh_t *) p->data);
}
wlc_print_txstatus(txs);
* Also initialize software state that depends on the particular hardware
* we are running.
*/
- wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
+ wlc_hw->sih = si_attach((uint) device, regsva, bustype, btparam,
&wlc_hw->vars, &wlc_hw->vars_size);
if (wlc_hw->sih == NULL) {
WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
/* Prototypes */
extern int srom_var_init(si_t *sih, uint bus, void *curmap,
- struct osl_info *osh, char **vars, uint *count);
+ char **vars, uint *count);
-extern int srom_read(si_t *sih, uint bus, void *curmap, struct osl_info *osh,
+extern int srom_read(si_t *sih, uint bus, void *curmap,
uint byteoff, uint nbytes, u16 *buf, bool check_crc);
/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
* and extract from it into name=value pairs
*/
-extern int srom_parsecis(struct osl_info *osh, u8 **pcis, uint ciscnt,
+extern int srom_parsecis(u8 **pcis, uint ciscnt,
char **vars, uint *count);
#endif /* _bcmsrom_h_ */
/* externs */
/* packet */
- extern uint pktfrombuf(struct osl_info *osh, struct sk_buff *p,
+ extern uint pktfrombuf(struct sk_buff *p,
uint offset, int len, unsigned char *buf);
extern uint pkttotlen(struct sk_buff *p);
extern char *getvar(char *vars, const char *name);
extern int getintvar(char *vars, const char *name);
#ifdef BCMDBG
- extern void prpkt(const char *msg, struct osl_info *osh,
- struct sk_buff *p0);
+ extern void prpkt(const char *msg, struct sk_buff *p0);
#else
-#define prpkt(a, b, c)
+#define prpkt(a, b)
#endif /* BCMDBG */
#define bcm_perf_enable()
#define SET_LDO_VOLTAGE_LNLDO1 9
#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
-extern void si_pmu_init(si_t *sih, struct osl_info *osh);
-extern void si_pmu_chip_init(si_t *sih, struct osl_info *osh);
-extern void si_pmu_pll_init(si_t *sih, struct osl_info *osh, u32 xtalfreq);
-extern void si_pmu_res_init(si_t *sih, struct osl_info *osh);
-extern void si_pmu_swreg_init(si_t *sih, struct osl_info *osh);
+extern void si_pmu_init(si_t *sih);
+extern void si_pmu_chip_init(si_t *sih);
+extern void si_pmu_pll_init(si_t *sih, u32 xtalfreq);
+extern void si_pmu_res_init(si_t *sih);
+extern void si_pmu_swreg_init(si_t *sih);
-extern u32 si_pmu_force_ilp(si_t *sih, struct osl_info *osh, bool force);
+extern u32 si_pmu_force_ilp(si_t *sih, bool force);
-extern u32 si_pmu_si_clock(si_t *sih, struct osl_info *osh);
-extern u32 si_pmu_cpu_clock(si_t *sih, struct osl_info *osh);
-extern u32 si_pmu_mem_clock(si_t *sih, struct osl_info *osh);
-extern u32 si_pmu_alp_clock(si_t *sih, struct osl_info *osh);
-extern u32 si_pmu_ilp_clock(si_t *sih, struct osl_info *osh);
+extern u32 si_pmu_si_clock(si_t *sih);
+extern u32 si_pmu_cpu_clock(si_t *sih);
+extern u32 si_pmu_mem_clock(si_t *sih);
+extern u32 si_pmu_alp_clock(si_t *sih);
+extern u32 si_pmu_ilp_clock(si_t *sih);
-extern void si_pmu_set_switcher_voltage(si_t *sih, struct osl_info *osh,
+extern void si_pmu_set_switcher_voltage(si_t *sih,
u8 bb_voltage, u8 rf_voltage);
-extern void si_pmu_set_ldo_voltage(si_t *sih, struct osl_info *osh, u8 ldo,
- u8 voltage);
-extern u16 si_pmu_fast_pwrup_delay(si_t *sih, struct osl_info *osh);
-extern void si_pmu_rcal(si_t *sih, struct osl_info *osh);
+extern void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage);
+extern u16 si_pmu_fast_pwrup_delay(si_t *sih);
+extern void si_pmu_rcal(si_t *sih);
extern void si_pmu_pllupd(si_t *sih);
-extern void si_pmu_spuravoid(si_t *sih, struct osl_info *osh, u8 spuravoid);
+extern void si_pmu_spuravoid(si_t *sih, u8 spuravoid);
-extern bool si_pmu_is_otp_powered(si_t *sih, struct osl_info *osh);
-extern u32 si_pmu_measure_alpclk(si_t *sih, struct osl_info *osh);
+extern bool si_pmu_is_otp_powered(si_t *sih);
+extern u32 si_pmu_measure_alpclk(si_t *sih);
extern u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern void si_pmu_pllupd(si_t *sih);
-extern void si_pmu_sprom_enable(si_t *sih, struct osl_info *osh, bool enable);
+extern void si_pmu_sprom_enable(si_t *sih, bool enable);
extern void si_pmu_radio_enable(si_t *sih, bool enable);
-extern u32 si_pmu_waitforclk_on_backplane(si_t *sih, struct osl_info *osh,
- u32 clk, u32 delay);
+extern u32 si_pmu_waitforclk_on_backplane(si_t *sih, u32 clk, u32 delay);
-extern void si_pmu_otp_power(si_t *sih, struct osl_info *osh, bool on);
-extern void si_sdiod_drive_strength_init(si_t *sih, struct osl_info *osh,
- u32 drivestrength);
+extern void si_pmu_otp_power(si_t *sih, bool on);
+extern void si_sdiod_drive_strength_init(si_t *sih, u32 drivestrength);
#endif /* _hndpmu_h_ */
extern u8 pcicore_find_pci_capability(void *dev, u8 req_cap_id,
unsigned char *buf, u32 *buflen);
-extern uint pcie_readreg(struct osl_info *osh, struct sbpcieregs *pcieregs,
+extern uint pcie_readreg(struct sbpcieregs *pcieregs,
uint addrtype, uint offset);
-extern uint pcie_writereg(struct osl_info *osh, struct sbpcieregs *pcieregs,
+extern uint pcie_writereg(struct sbpcieregs *pcieregs,
uint addrtype, uint offset, uint val);
extern u8 pcie_clkreq(void *pch, u32 mask, u32 val);
extern u32 pcie_lcreg(void *pch, u32 mask, u32 val);
-extern void *pcicore_init(si_t *sih, struct osl_info *osh, void *regs);
+extern void *pcicore_init(si_t *sih, void *pdev, void *regs);
extern void pcicore_deinit(void *pch);
extern void pcicore_attach(void *pch, char *pvars, int state);
extern void pcicore_hwup(void *pch);
#define GPIO_CTRL_EPA_EN_MASK 0x40
/* === exported functions === */
-extern si_t *si_attach(uint pcidev, struct osl_info *osh, void *regs,
- uint bustype, void *sdh, char **vars, uint *varsz);
+extern si_t *si_attach(uint pcidev, void *regs, uint bustype,
+ void *sdh, char **vars, uint *varsz);
extern void si_detach(si_t *sih);
extern bool si_pci_war16165(si_t *sih);
extern uint si_flag(si_t *sih);
extern uint si_coreidx(si_t *sih);
extern uint si_corerev(si_t *sih);
-struct osl_info *si_osh(si_t *sih);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
uint val);
extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
/* misc si info needed by some of the routines */
typedef struct si_info {
struct si_pub pub; /* back plane public state (must be first) */
- struct osl_info *osh; /* osl os handle */
void *pbus; /* handle to bus (pci/sdio/..) */
uint dev_coreid; /* the core provides driver functions */
void *intr_arg; /* interrupt callback function arg */
uint ccrev; /* chipc revision */
otp_fn_t *fn; /* OTP functions */
si_t *sih; /* Saved sb handle */
- struct osl_info *osh;
#ifdef BCMIPXOTP
/* IPX OTP section */
static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
{
+#ifdef BCMDBG
otpinfo_t *oi = (otpinfo_t *) oh;
- struct osl_info *osh;
+#endif
volatile u16 *ptr;
ASSERT(wn < ((oi->size / 2) + OTP_RC_LIM_OFF));
ASSERT(cc != NULL);
- osh = si_osh(oi->sih);
-
ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
return R_REG(&ptr[wn]);
}
static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
{
otpinfo_t *oi = (otpinfo_t *) oh;
- struct osl_info *osh;
volatile u16 *ptr;
ASSERT(woff >= (-((int)oi->size / 2)));
ASSERT(woff < OTP_LIM_OFF);
ASSERT(cc != NULL);
- osh = si_osh(oi->sih);
-
ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
return R_REG(&ptr[(oi->size / 2) + woff]);
static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
{
- otpinfo_t *oi = (otpinfo_t *) oh;
uint k, row, col;
u32 otpp, st;
- struct osl_info *osh;
- osh = si_osh(oi->sih);
row = idx / 65;
col = idx % 65;
otpinfo_t *oi;
u32 cap = 0, clkdiv, otpdiv = 0;
void *ret = NULL;
- struct osl_info *osh;
oi = &otpinfo;
idx = si_coreidx(sih);
- osh = si_osh(oi->sih);
/* Check for otp */
cc = si_setcoreidx(sih, SI_CC_IDX);
}
oi->sih = sih;
- oi->osh = si_osh(oi->sih);
ret = (oi->fn->init) (sih);
#define SROM_CIS_SINGLE 1
-static int initvars_srom_si(si_t *sih, struct osl_info *osh, void *curmap,
- char **vars, uint *count);
-static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off,
- varbuf_t *b);
-static int initvars_srom_pci(si_t *sih, void *curmap, char **vars,
- uint *count);
+static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *count);
+static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
+static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count);
static int initvars_flash_si(si_t *sih, char **vars, uint *count);
#ifdef BCMSDIO
-static int initvars_cis_sdio(struct osl_info *osh, char **vars, uint *count);
-static int sprom_cmd_sdio(struct osl_info *osh, u8 cmd);
-static int sprom_read_sdio(struct osl_info *osh, u16 addr, u16 *data);
+static int initvars_cis_sdio(char **vars, uint *count);
+static int sprom_cmd_sdio(u8 cmd);
+static int sprom_read_sdio(u16 addr, u16 *data);
#endif /* BCMSDIO */
-static int sprom_read_pci(struct osl_info *osh, si_t *sih, u16 *sprom,
+static int sprom_read_pci(si_t *sih, u16 *sprom,
uint wordoff, u16 *buf, uint nwords, bool check_crc);
#if defined(BCMNVRAMR)
-static int otp_read_pci(struct osl_info *osh, si_t *sih, u16 *buf, uint bufsz);
+static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz);
#endif
-static u16 srom_cc_cmd(si_t *sih, struct osl_info *osh, void *ccregs, u32 cmd,
+static u16 srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
uint wordoff, u16 data);
-static int initvars_table(struct osl_info *osh, char *start, char *end,
+static int initvars_table(char *start, char *end,
char **vars, uint *count);
-static int initvars_flash(si_t *sih, struct osl_info *osh, char **vp,
+static int initvars_flash(si_t *sih, char **vp,
uint len);
/* Initialization of varbuf structure */
* Initialize local vars from the right source for this platform.
* Return 0 on success, nonzero on error.
*/
-int srom_var_init(si_t *sih, uint bustype, void *curmap, struct osl_info *osh,
+int srom_var_init(si_t *sih, uint bustype, void *curmap,
char **vars, uint *count)
{
uint len;
switch (bustype) {
case SI_BUS:
case JTAG_BUS:
- return initvars_srom_si(sih, osh, curmap, vars, count);
+ return initvars_srom_si(sih, curmap, vars, count);
case PCI_BUS:
ASSERT(curmap != NULL);
#ifdef BCMSDIO
case SDIO_BUS:
- return initvars_cis_sdio(osh, vars, count);
+ return initvars_cis_sdio(vars, count);
#endif /* BCMSDIO */
default:
/* support only 16-bit word read from srom */
int
-srom_read(si_t *sih, uint bustype, void *curmap, struct osl_info *osh,
+srom_read(si_t *sih, uint bustype, void *curmap,
uint byteoff, uint nbytes, u16 *buf, bool check_crc)
{
uint off, nw;
return 1;
if (sprom_read_pci
- (osh, sih, srom, off, buf, nw, check_crc))
+ (sih, srom, off, buf, nw, check_crc))
return 1;
}
#if defined(BCMNVRAMR)
else {
- if (otp_read_pci(osh, sih, buf, SROM_MAX))
+ if (otp_read_pci(sih, buf, SROM_MAX))
return 1;
}
#endif
nw = nbytes / 2;
for (i = 0; i < nw; i++) {
if (sprom_read_sdio
- (osh, (u16) (off + i), (u16 *) (buf + i)))
+ ((u16) (off + i), (u16 *) (buf + i)))
return 1;
}
#endif /* BCMSDIO */
/* For dongle HW, accept partial calibration parameters */
#define BCMDONGLECASE(n)
-int srom_parsecis(struct osl_info *osh, u8 *pcis[], uint ciscnt, char **vars,
+int srom_parsecis(u8 *pcis[], uint ciscnt, char **vars,
uint *count)
{
char eabuf[32];
*b.buf++ = '\0';
ASSERT(b.buf - base <= MAXSZ_NVRAM_VARS);
- err = initvars_table(osh, base, b.buf, vars, count);
+ err = initvars_table(base, b.buf, vars, count);
kfree(base);
return err;
* not in the bus cores.
*/
static u16
-srom_cc_cmd(si_t *sih, struct osl_info *osh, void *ccregs, u32 cmd,
+srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
uint wordoff, u16 data)
{
chipcregs_t *cc = (chipcregs_t *) ccregs;
* Return 0 on success, nonzero on error.
*/
static int
-sprom_read_pci(struct osl_info *osh, si_t *sih, u16 *sprom, uint wordoff,
+sprom_read_pci(si_t *sih, u16 *sprom, uint wordoff,
u16 *buf, uint nwords, bool check_crc)
{
int err = 0;
ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
buf[i] =
- srom_cc_cmd(sih, osh, ccregs, SRC_OP_READ,
+ srom_cc_cmd(sih, ccregs, SRC_OP_READ,
wordoff + i, 0);
} else {
}
#if defined(BCMNVRAMR)
-static int otp_read_pci(struct osl_info *osh, si_t *sih, u16 *buf, uint bufsz)
+static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz)
{
u8 *otp;
uint sz = OTP_SZ_MAX / 2; /* size in words */
* Create variable table from memory.
* Return 0 on success, nonzero on error.
*/
-static int initvars_table(struct osl_info *osh, char *start, char *end,
+static int initvars_table(char *start, char *end,
char **vars, uint *count)
{
int c = (int)(end - start);
* of the table upon enter and to the end of the table upon exit when success.
* Return 0 on success, nonzero on error.
*/
-static int initvars_flash(si_t *sih, struct osl_info *osh, char **base,
- uint len)
+static int initvars_flash(si_t *sih, char **base, uint len)
{
char *vp = *base;
char *flash;
*/
static int initvars_flash_si(si_t *sih, char **vars, uint *count)
{
- struct osl_info *osh = si_osh(sih);
char *vp, *base;
int err;
if (!vp)
return BCME_NOMEM;
- err = initvars_flash(sih, osh, &vp, MAXSZ_NVRAM_VARS);
+ err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
if (err == 0)
- err = initvars_table(osh, base, vp, vars, count);
+ err = initvars_table(base, vp, vars, count);
kfree(base);
u32 sr;
varbuf_t b;
char *vp, *base = NULL;
- struct osl_info *osh = si_osh(sih);
bool flash = false;
int err = 0;
sromwindow = (u16 *) SROM_OFFSET(sih);
if (si_is_sprom_available(sih)) {
err =
- sprom_read_pci(osh, sih, sromwindow, 0, srom, SROM_WORDS,
+ sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
true);
if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
&& (sih->buscorerev >= 0xe)))) {
/* sromrev >= 4, read more */
err =
- sprom_read_pci(osh, sih, sromwindow, 0, srom,
+ sprom_read_pci(sih, sromwindow, 0, srom,
SROM4_WORDS, true);
sromrev = srom[SROM4_CRCREV] & 0xff;
if (err)
}
#if defined(BCMNVRAMR)
/* Use OTP if SPROM not available */
- else if ((err = otp_read_pci(osh, sih, srom, SROM_MAX)) == 0) {
- /* OTP only contain SROM rev8/rev9 for now */
- sromrev = srom[SROM4_CRCREV] & 0xff;
- }
-#endif
else {
- err = 1;
- BS_ERROR(("Neither SPROM nor OTP has valid image\n"));
+ err = otp_read_pci(sih, srom, SROM_MAX);
+ if (err == 0)
+ /* OTP only contain SROM rev8/rev9 for now */
+ sromrev = srom[SROM4_CRCREV] & 0xff;
+ else
+ err = 1;
}
+#else
+ else
+ err = 1;
+#endif
- /* We want internal/wltest driver to come up with default sromvars so we can
- * program a blank SPROM/OTP.
+ /*
+ * We want internal/wltest driver to come up with default
+ * sromvars so we can program a blank SPROM/OTP.
*/
if (err) {
char *value;
u32 val;
val = 0;
+ BS_ERROR(("Neither SPROM nor OTP has valid image\n"));
value = si_getdevpathvar(sih, "sromrev");
if (value) {
sromrev = (u8) simple_strtoul(value, NULL, 0);
/* read variables from flash */
if (flash) {
- err = initvars_flash(sih, osh, &vp, MAXSZ_NVRAM_VARS);
+ err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
if (err)
goto errout;
goto varsdone;
ASSERT((vp - base) <= MAXSZ_NVRAM_VARS);
varsdone:
- err = initvars_table(osh, base, vp, vars, count);
+ err = initvars_table(base, vp, vars, count);
errout:
if (base)
* Read the SDIO cis and call parsecis to initialize the vars.
* Return 0 on success, nonzero on error.
*/
-static int initvars_cis_sdio(struct osl_info *osh, char **vars, uint *count)
+static int initvars_cis_sdio(char **vars, uint *count)
{
u8 *cis[SBSDIO_NUM_FUNCTION + 1];
uint fn, numfn;
}
if (!rc)
- rc = srom_parsecis(osh, cis, fn, vars, count);
+ rc = srom_parsecis(cis, fn, vars, count);
while (fn-- > 0)
kfree(cis[fn]);
}
/* set SDIO sprom command register */
-static int sprom_cmd_sdio(struct osl_info *osh, u8 cmd)
+static int sprom_cmd_sdio(u8 cmd)
{
u8 status = 0;
uint wait_cnt = 1000;
}
/* read a word from the SDIO srom */
-static int sprom_read_sdio(struct osl_info *osh, u16 addr, u16 *data)
+static int sprom_read_sdio(u16 addr, u16 *data)
{
u8 addr_l, addr_h, data_l, data_h;
NULL);
/* do read */
- if (sprom_cmd_sdio(osh, SBSDIO_SPROM_READ))
+ if (sprom_cmd_sdio(SBSDIO_SPROM_READ))
return 1;
/* read data */
}
#endif /* BCMSDIO */
-static int initvars_srom_si(si_t *sih, struct osl_info *osh, void *curmap,
- char **vars, uint *varsz)
+static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *varsz)
{
/* Search flash nvram section for srom variables */
return initvars_flash_si(sih, vars, varsz);
}
/* copy a buffer into a pkt buffer chain */
-uint pktfrombuf(struct osl_info *osh, struct sk_buff *p, uint offset, int len,
+uint pktfrombuf(struct sk_buff *p, uint offset, int len,
unsigned char *buf)
{
uint n, ret = 0;
#if defined(BCMDBG)
/* pretty hex print a pkt buffer chain */
-void prpkt(const char *msg, struct osl_info *osh, struct sk_buff *p0)
+void prpkt(const char *msg, struct sk_buff *p0)
{
struct sk_buff *p;
static bool dma64_txstopped(dma_info_t *di);
static bool dma64_rxstopped(dma_info_t *di);
static bool dma64_rxenabled(dma_info_t *di);
-static bool _dma64_addrext(struct osl_info *osh, dma64regs_t *dma64regs);
+static bool _dma64_addrext(dma64regs_t *dma64regs);
static inline u32 parity32(u32 data);
/* not all tx or rx channel are available */
if (di->d64txregs != NULL) {
- if (!_dma64_addrext(di->osh, di->d64txregs)) {
+ if (!_dma64_addrext(di->d64txregs)) {
DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
"AE set\n", di->name));
ASSERT(0);
}
return true;
} else if (di->d64rxregs != NULL) {
- if (!_dma64_addrext(di->osh, di->d64rxregs)) {
+ if (!_dma64_addrext(di->d64rxregs)) {
DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
"AE set\n", di->name));
ASSERT(0);
return rxp;
}
-static bool _dma64_addrext(struct osl_info *osh, dma64regs_t * dma64regs)
+static bool _dma64_addrext(dma64regs_t *dma64regs)
{
u32 w;
OR_REG(&dma64regs->control, D64_XC_AE);
uint dma_addrwidth(si_t *sih, void *dmaregs)
{
- struct osl_info *osh;
-
- osh = si_osh(sih);
-
/* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
/* DMA engine is 64-bit capable */
if ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
#define PMU_NONE(args)
/* PLL controls/clocks */
-static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
- u32 xtal);
-static u32 si_pmu1_cpuclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc);
-static u32 si_pmu1_alpclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc);
+static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal);
+static u32 si_pmu1_cpuclk0(si_t *sih, chipcregs_t *cc);
+static u32 si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc);
/* PMU resources */
static bool si_pmu_res_depfltr_bb(si_t *sih);
static bool si_pmu_res_depfltr_ncb(si_t *sih);
static bool si_pmu_res_depfltr_paldo(si_t *sih);
static bool si_pmu_res_depfltr_npaldo(si_t *sih);
-static u32 si_pmu_res_deps(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
- u32 rsrcs, bool all);
-static uint si_pmu_res_uptime(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
- u8 rsrc);
+static u32 si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs, bool all);
+static uint si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc);
static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
- struct osl_info *osh, u8 spuravoid);
+ u8 spuravoid);
static void si_pmu_set_4330_plldivs(si_t *sih);
}
/* Setup switcher voltage */
-void si_pmu_set_switcher_voltage(si_t *sih, struct osl_info *osh, u8 bb_voltage,
- u8 rf_voltage)
+void si_pmu_set_switcher_voltage(si_t *sih, u8 bb_voltage, u8 rf_voltage)
{
chipcregs_t *cc;
uint origidx;
si_setcoreidx(sih, origidx);
}
-void si_pmu_set_ldo_voltage(si_t *sih, struct osl_info *osh, u8 ldo, u8 voltage)
+void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage)
{
u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
u8 addr = 0;
/* d11 slow to fast clock transition time in slow clock cycles */
#define D11SCC_SLOW2FAST_TRANSITION 2
-u16 si_pmu_fast_pwrup_delay(si_t *sih, struct osl_info *osh)
+u16 si_pmu_fast_pwrup_delay(si_t *sih)
{
uint delay = PMU_MAX_TRANSITION_DLY;
chipcregs_t *cc;
else {
u32 ilp = si_ilp_clock(sih);
delay =
- (si_pmu_res_uptime(sih, osh, cc, RES4329_HT_AVAIL) +
+ (si_pmu_res_uptime(sih, cc, RES4329_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
1) / ilp);
delay = (11 * delay) / 10;
else {
u32 ilp = si_ilp_clock(sih);
delay =
- (si_pmu_res_uptime(sih, osh, cc, RES4336_HT_AVAIL) +
+ (si_pmu_res_uptime(sih, cc, RES4336_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
1) / ilp);
delay = (11 * delay) / 10;
else {
u32 ilp = si_ilp_clock(sih);
delay =
- (si_pmu_res_uptime(sih, osh, cc, RES4330_HT_AVAIL) +
+ (si_pmu_res_uptime(sih, cc, RES4330_HT_AVAIL) +
D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
1) / ilp);
delay = (11 * delay) / 10;
return (u16) delay;
}
-u32 si_pmu_force_ilp(si_t *sih, struct osl_info *osh, bool force)
+u32 si_pmu_force_ilp(si_t *sih, bool force)
{
chipcregs_t *cc;
uint origidx;
}
/* initialize PMU resources */
-void si_pmu_res_init(si_t *sih, struct osl_info *osh)
+void si_pmu_res_init(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
/* query alp/xtal clock frequency */
static u32
-si_pmu1_alpclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc)
+si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc)
{
const pmu1_xtaltab0_t *xt;
u32 xf;
* case the xtal frequency is unknown to the s/w so we need to call
* si_pmu1_xtaldef0() wherever it is needed to return a default value.
*/
-static void si_pmu1_pllinit0(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
- u32 xtal)
+static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal)
{
const pmu1_xtaltab0_t *xt;
u32 tmp;
/* query the CPU clock frequency */
static u32
-si_pmu1_cpuclk0(si_t *sih, struct osl_info *osh, chipcregs_t *cc)
+si_pmu1_cpuclk0(si_t *sih, chipcregs_t *cc)
{
u32 tmp, m1div;
#ifdef BCMDBG
(tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >>
PMU1_PLL0_PC3_NDIV_FRAC_SHIFT;
- fref = si_pmu1_alpclk0(sih, osh, cc) / 1000;
+ fref = si_pmu1_alpclk0(sih, cc) / 1000;
fvco = (fref * ndiv_int) << 8;
fvco += (fref * (ndiv_frac >> 12)) >> 4;
}
/* initialize PLL */
-void si_pmu_pll_init(si_t *sih, struct osl_info *osh, uint xtalfreq)
+void si_pmu_pll_init(si_t *sih, uint xtalfreq)
{
chipcregs_t *cc;
uint origidx;
case BCM4329_CHIP_ID:
if (xtalfreq == 0)
xtalfreq = 38400;
- si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
+ si_pmu1_pllinit0(sih, cc, xtalfreq);
break;
case BCM4313_CHIP_ID:
case BCM43224_CHIP_ID:
case BCM4319_CHIP_ID:
case BCM4336_CHIP_ID:
case BCM4330_CHIP_ID:
- si_pmu1_pllinit0(sih, osh, cc, xtalfreq);
+ si_pmu1_pllinit0(sih, cc, xtalfreq);
break;
default:
PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n",
}
/* query alp/xtal clock frequency */
-u32 si_pmu_alp_clock(si_t *sih, struct osl_info *osh)
+u32 si_pmu_alp_clock(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
case BCM4336_CHIP_ID:
case BCM4330_CHIP_ID:
- clock = si_pmu1_alpclk0(sih, osh, cc);
+ clock = si_pmu1_alpclk0(sih, cc);
break;
case BCM5356_CHIP_ID:
/* always 25Mhz */
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
*/
static u32
-si_pmu5_clock(si_t *sih, struct osl_info *osh, chipcregs_t *cc, uint pll0,
- uint m) {
+si_pmu5_clock(si_t *sih, chipcregs_t *cc, uint pll0, uint m) {
u32 tmp, div, ndiv, p1, p2, fc;
if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT;
/* Do calculation in Mhz */
- fc = si_pmu_alp_clock(sih, osh) / 1000000;
+ fc = si_pmu_alp_clock(sih) / 1000000;
fc = (p1 * ndiv * fc) / p2;
PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n",
/* For designs that feed the same clock to both backplane
* and CPU just return the CPU clock speed.
*/
-u32 si_pmu_si_clock(si_t *sih, struct osl_info *osh)
+u32 si_pmu_si_clock(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
case BCM4748_CHIP_ID:
case BCM47162_CHIP_ID:
clock =
- si_pmu5_clock(sih, osh, cc, PMU4716_MAINPLL_PLL0,
+ si_pmu5_clock(sih, cc, PMU4716_MAINPLL_PLL0,
PMU5_MAINPLL_SI);
break;
case BCM4329_CHIP_ID:
if (sih->chiprev == 0)
clock = 38400 * 1000;
else
- clock = si_pmu1_cpuclk0(sih, osh, cc);
+ clock = si_pmu1_cpuclk0(sih, cc);
break;
case BCM4319_CHIP_ID:
case BCM4336_CHIP_ID:
case BCM4330_CHIP_ID:
- clock = si_pmu1_cpuclk0(sih, osh, cc);
+ clock = si_pmu1_cpuclk0(sih, cc);
break;
case BCM4313_CHIP_ID:
/* 80MHz backplane clock */
break;
case BCM5356_CHIP_ID:
clock =
- si_pmu5_clock(sih, osh, cc, PMU5356_MAINPLL_PLL0,
+ si_pmu5_clock(sih, cc, PMU5356_MAINPLL_PLL0,
PMU5_MAINPLL_SI);
break;
case BCM5357_CHIP_ID:
clock =
- si_pmu5_clock(sih, osh, cc, PMU5357_MAINPLL_PLL0,
+ si_pmu5_clock(sih, cc, PMU5357_MAINPLL_PLL0,
PMU5_MAINPLL_SI);
break;
default:
}
/* query CPU clock frequency */
-u32 si_pmu_cpu_clock(si_t *sih, struct osl_info *osh)
+u32 si_pmu_cpu_clock(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
cc = si_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc != NULL);
- clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_CPU);
+ clock = si_pmu5_clock(sih, cc, pll, PMU5_MAINPLL_CPU);
/* Return to original core */
si_setcoreidx(sih, origidx);
} else
- clock = si_pmu_si_clock(sih, osh);
+ clock = si_pmu_si_clock(sih);
return clock;
}
/* query memory clock frequency */
-u32 si_pmu_mem_clock(si_t *sih, struct osl_info *osh)
+u32 si_pmu_mem_clock(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
cc = si_setcoreidx(sih, SI_CC_IDX);
ASSERT(cc != NULL);
- clock = si_pmu5_clock(sih, osh, cc, pll, PMU5_MAINPLL_MEM);
+ clock = si_pmu5_clock(sih, cc, pll, PMU5_MAINPLL_MEM);
/* Return to original core */
si_setcoreidx(sih, origidx);
} else {
- clock = si_pmu_si_clock(sih, osh);
+ clock = si_pmu_si_clock(sih);
}
return clock;
static u32 ilpcycles_per_sec;
-u32 si_pmu_ilp_clock(si_t *sih, struct osl_info *osh)
+u32 si_pmu_ilp_clock(si_t *sih)
{
if (ISSIM_ENAB(sih))
return ILP_CLOCK;
#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
void
-si_sdiod_drive_strength_init(si_t *sih, struct osl_info *osh,
- u32 drivestrength) {
+si_sdiod_drive_strength_init(si_t *sih, u32 drivestrength) {
chipcregs_t *cc;
uint origidx, intr_val = 0;
sdiod_drive_str_t *str_tab = NULL;
}
/* initialize PMU */
-void si_pmu_init(si_t *sih, struct osl_info *osh)
+void si_pmu_init(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
/* Return up time in ILP cycles for the given resource. */
static uint
-si_pmu_res_uptime(si_t *sih, struct osl_info *osh, chipcregs_t *cc,
- u8 rsrc) {
+si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc) {
u32 deps;
uint up, i, dup, dmax;
u32 min_mask = 0, max_mask = 0;
up = (R_REG(&cc->res_updn_timer) >> 8) & 0xff;
/* direct dependancies of resource 'rsrc' */
- deps = si_pmu_res_deps(sih, osh, cc, PMURES_BIT(rsrc), false);
+ deps = si_pmu_res_deps(sih, cc, PMURES_BIT(rsrc), false);
for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
if (!(deps & PMURES_BIT(i)))
continue;
- deps &= ~si_pmu_res_deps(sih, osh, cc, PMURES_BIT(i), true);
+ deps &= ~si_pmu_res_deps(sih, cc, PMURES_BIT(i), true);
}
si_pmu_res_masks(sih, &min_mask, &max_mask);
deps &= ~min_mask;
for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
if (!(deps & PMURES_BIT(i)))
continue;
- dup = si_pmu_res_uptime(sih, osh, cc, (u8) i);
+ dup = si_pmu_res_uptime(sih, cc, (u8) i);
if (dmax < dup)
dmax = dup;
}
/* Return dependancies (direct or all/indirect) for the given resources */
static u32
-si_pmu_res_deps(si_t *sih, struct osl_info *osh, chipcregs_t *cc, u32 rsrcs,
+si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs,
bool all)
{
u32 deps = 0;
return !all ? deps : (deps
? (deps |
- si_pmu_res_deps(sih, osh, cc, deps,
+ si_pmu_res_deps(sih, cc, deps,
true)) : 0);
}
/* power up/down OTP through PMU resources */
-void si_pmu_otp_power(si_t *sih, struct osl_info *osh, bool on)
+void si_pmu_otp_power(si_t *sih, bool on)
{
chipcregs_t *cc;
uint origidx;
u32 otps;
/* Figure out the dependancies (exclude min_res_mask) */
- u32 deps = si_pmu_res_deps(sih, osh, cc, rsrcs, true);
+ u32 deps = si_pmu_res_deps(sih, cc, rsrcs, true);
u32 min_mask = 0, max_mask = 0;
si_pmu_res_masks(sih, &min_mask, &max_mask);
deps &= ~min_mask;
si_setcoreidx(sih, origidx);
}
-void si_pmu_rcal(si_t *sih, struct osl_info *osh)
+void si_pmu_rcal(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
si_setcoreidx(sih, origidx);
}
-void si_pmu_spuravoid(si_t *sih, struct osl_info *osh, u8 spuravoid)
+void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
{
chipcregs_t *cc;
uint origidx, intr_val;
}
/* update the pll changes */
- si_pmu_spuravoid_pllupdate(sih, cc, osh, spuravoid);
+ si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
/* enable HT back on */
if (sih->chip == BCM4336_CHIP_ID) {
}
static void
-si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, struct osl_info *osh,
- u8 spuravoid)
+si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
{
u32 tmp = 0;
u8 phypll_offset = 0;
W_REG(&cc->pmucontrol, tmp);
}
-bool si_pmu_is_otp_powered(si_t *sih, struct osl_info *osh)
+bool si_pmu_is_otp_powered(si_t *sih)
{
uint idx;
chipcregs_t *cc;
return st;
}
-void si_pmu_sprom_enable(si_t *sih, struct osl_info *osh, bool enable)
+void si_pmu_sprom_enable(si_t *sih, bool enable)
{
chipcregs_t *cc;
uint origidx;
}
/* initialize PMU chip controls and other chip level stuff */
-void si_pmu_chip_init(si_t *sih, struct osl_info *osh)
+void si_pmu_chip_init(si_t *sih)
{
uint origidx;
#endif /* CHIPC_UART_ALWAYS_ON */
/* Gate off SPROM clock and chip select signals */
- si_pmu_sprom_enable(sih, osh, false);
+ si_pmu_sprom_enable(sih, false);
/* Remember original core */
origidx = si_coreidx(sih);
}
/* initialize PMU switch/regulators */
-void si_pmu_swreg_init(si_t *sih, struct osl_info *osh)
+void si_pmu_swreg_init(si_t *sih)
{
ASSERT(sih->cccaps & CC_CAP_PMU);
switch (sih->chip) {
case BCM4336_CHIP_ID:
/* Reduce CLDO PWM output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
/* Reduce CLDO BURST output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CLDO_BURST,
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_BURST,
0xe);
/* Reduce LNLDO1 output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_LNLDO1, 0xe);
if (sih->chiprev == 0)
si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
break;
case BCM4330_CHIP_ID:
/* CBUCK Voltage is 1.8 by default and set that to 1.5 */
- si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
break;
default:
break;
/* Wait for a particular clock level to be on the backplane */
u32
-si_pmu_waitforclk_on_backplane(si_t *sih, struct osl_info *osh, u32 clk,
- u32 delay)
+si_pmu_waitforclk_on_backplane(si_t *sih, u32 clk, u32 delay)
{
chipcregs_t *cc;
uint origidx;
#define EXT_ILP_HZ 32768
-u32 si_pmu_measure_alpclk(si_t *sih, struct osl_info *osh)
+u32 si_pmu_measure_alpclk(si_t *sih)
{
chipcregs_t *cc;
uint origidx;
si_t *sih; /* System interconnect handle */
struct pci_dev *dev;
- struct osl_info *osh; /* OSL handle */
u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
bool pcie_pr42767;
u8 pcie_polarity;
/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
* only once
*/
-void *pcicore_init(si_t *sih, struct osl_info *osh, void *regs)
+void *pcicore_init(si_t *sih, void *pdev, void *regs)
{
pcicore_info_t *pi;
}
pi->sih = sih;
- pi->osh = osh;
- pi->dev = osh->pdev;
+ pi->dev = pdev;
if (sih->buscoretype == PCIE_CORE_ID) {
u8 cap_ptr;
/* ***** Register Access API */
uint
-pcie_readreg(struct osl_info *osh, sbpcieregs_t *pcieregs, uint addrtype,
+pcie_readreg(sbpcieregs_t *pcieregs, uint addrtype,
uint offset)
{
uint retval = 0xFFFFFFFF;
}
uint
-pcie_writereg(struct osl_info *osh, sbpcieregs_t *pcieregs, uint addrtype,
+pcie_writereg(sbpcieregs_t *pcieregs, uint addrtype,
uint offset, uint val)
{
ASSERT(pcieregs != NULL);
{
u32 w;
si_t *sih = pi->sih;
- struct osl_info *osh = pi->osh;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
if (!PCIE_PUB(sih) || sih->buscorerev < 7)
return;
- w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
if (extend)
w |= PCIE_ASPMTIMER_EXTEND;
else
w &= ~PCIE_ASPMTIMER_EXTEND;
- pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
- w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
+ pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
}
/* centralized clkreq control policy */
if (pi->pcie_polarity != 0)
return;
- w = pcie_readreg(pi->osh, pi->regs.pcieregs, PCIE_PCIEREGS,
+ w = pcie_readreg(pi->regs.pcieregs, PCIE_PCIEREGS,
PCIE_PLP_STATUSREG);
/* Detect the current polarity at attach and force that polarity and
static void pcie_war_pci_setup(pcicore_info_t *pi)
{
si_t *sih = pi->sih;
- struct osl_info *osh = pi->osh;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
u32 w;
if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
- w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
PCIE_TLP_WORKAROUNDSREG);
w |= 0x8;
- pcie_writereg(osh, pcieregs, PCIE_PCIEREGS,
+ pcie_writereg(pcieregs, PCIE_PCIEREGS,
PCIE_TLP_WORKAROUNDSREG, w);
}
if (sih->buscorerev == 1) {
- w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
w |= (0x40);
- pcie_writereg(osh, pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
+ pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
}
if (sih->buscorerev == 0) {
pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
} else if (PCIE_ASPM(sih)) {
/* Change the L1 threshold for better performance */
- w = pcie_readreg(osh, pcieregs, PCIE_PCIEREGS,
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
PCIE_DLLP_PMTHRESHREG);
w &= ~(PCIE_L1THRESHOLDTIME_MASK);
w |= (PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT);
- pcie_writereg(osh, pcieregs, PCIE_PCIEREGS,
+ pcie_writereg(pcieregs, PCIE_PCIEREGS,
PCIE_DLLP_PMTHRESHREG, w);
pcie_war_serdes(pi);
u32 reg_val = 0;
pcicore_info_t *pi = (pcicore_info_t *) pch;
sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- struct osl_info *osh = pi->osh;
if (mask) {
PCI_ERROR(("PCIEREG: 0x%x writeval 0x%x\n", offset, val));
- pcie_writereg(osh, pcieregs, type, offset, val);
+ pcie_writereg(pcieregs, type, offset, val);
}
/* Should not read register 0x154 */
&& type == PCIE_PCIEREGS)
return reg_val;
- reg_val = pcie_readreg(osh, pcieregs, type, offset);
+ reg_val = pcie_readreg(pcieregs, type, offset);
PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val));
return reg_val;
#endif
/* local prototypes */
-static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
- void *regs, uint bustype, void *sdh, char **vars,
+static si_info_t *si_doattach(si_info_t *sii, uint devid, void *regs,
+ uint bustype, void *sdh, char **vars,
uint *varsz);
static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
void *sdh);
* vars - pointer to a pointer area for "environment" variables
* varsz - pointer to int to return the size of the vars
*/
-si_t *si_attach(uint devid, struct osl_info *osh, void *regs, uint bustype,
+si_t *si_attach(uint devid, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz)
{
si_info_t *sii;
return NULL;
}
- if (si_doattach(sii, devid, osh, regs, bustype, sdh, vars, varsz) ==
+ if (si_doattach(sii, devid, regs, bustype, sdh, vars, varsz) ==
NULL) {
kfree(sii);
return NULL;
if (SI_FAST(sii)) {
if (!sii->pch) {
sii->pch = (void *)pcicore_init(
- &sii->pub, sii->osh,
+ &sii->pub, sii->pbus,
(void *)PCIEREGS(sii));
if (sii->pch == NULL)
return false;
/* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */
/* this has been customized for the bcm 4329 ONLY */
#ifdef BCMSDIO
-static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
+static si_info_t *si_doattach(si_info_t *sii, uint devid,
void *regs, uint bustype, void *pbus,
char **vars, uint *varsz)
{
sii->curmap = regs;
sii->pbus = pbus;
- sii->osh = osh;
/* find Chipcommon address */
cc = (chipcregs_t *) sii->curmap;
/* PMU specific initializations */
if (PMUCTL_ENAB(sih)) {
u32 xtalfreq;
- si_pmu_init(sih, sii->osh);
- si_pmu_chip_init(sih, sii->osh);
+ si_pmu_init(sih);
+ si_pmu_chip_init(sih);
xtalfreq = getintvar(pvars, "xtalfreq");
/* If xtalfreq var not available, try to measure it */
if (xtalfreq == 0)
- xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
- si_pmu_pll_init(sih, sii->osh, xtalfreq);
- si_pmu_res_init(sih, sii->osh);
- si_pmu_swreg_init(sih, sii->osh);
+ xtalfreq = si_pmu_measure_alpclk(sih);
+ si_pmu_pll_init(sih, xtalfreq);
+ si_pmu_res_init(sih);
+ si_pmu_swreg_init(sih);
}
/* setup the GPIO based LED powersave register */
}
#else /* BCMSDIO */
-static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
+static si_info_t *si_doattach(si_info_t *sii, uint devid,
void *regs, uint bustype, void *pbus,
char **vars, uint *varsz)
{
sii->curmap = regs;
sii->pbus = pbus;
- sii->osh = osh;
/* check to see if we are a si core mimic'ing a pci core */
if (bustype == PCI_BUS) {
/* Init nvram from sprom/otp if they exist */
if (srom_var_init
- (&sii->pub, bustype, regs, sii->osh, vars, varsz)) {
+ (&sii->pub, bustype, regs, vars, varsz)) {
SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
goto exit;
}
/* PMU specific initializations */
if (PMUCTL_ENAB(sih)) {
u32 xtalfreq;
- si_pmu_init(sih, sii->osh);
- si_pmu_chip_init(sih, sii->osh);
+ si_pmu_init(sih);
+ si_pmu_chip_init(sih);
xtalfreq = getintvar(pvars, "xtalfreq");
/* If xtalfreq var not available, try to measure it */
if (xtalfreq == 0)
- xtalfreq = si_pmu_measure_alpclk(sih, sii->osh);
- si_pmu_pll_init(sih, sii->osh, xtalfreq);
- si_pmu_res_init(sih, sii->osh);
- si_pmu_swreg_init(sih, sii->osh);
+ xtalfreq = si_pmu_measure_alpclk(sih);
+ si_pmu_pll_init(sih, xtalfreq);
+ si_pmu_res_init(sih);
+ si_pmu_swreg_init(sih);
}
/* setup the GPIO based LED powersave register */
kfree(sii);
}
-struct osl_info *si_osh(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- return sii->osh;
-}
-
/* register driver interrupt disabling and restoring callback functions */
void
si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
u32 si_alp_clock(si_t *sih)
{
if (PMUCTL_ENAB(sih))
- return si_pmu_alp_clock(sih, si_osh(sih));
+ return si_pmu_alp_clock(sih);
return ALP_CLOCK;
}
u32 si_ilp_clock(si_t *sih)
{
if (PMUCTL_ENAB(sih))
- return si_pmu_ilp_clock(sih, si_osh(sih));
+ return si_pmu_ilp_clock(sih);
return ILP_CLOCK;
}
sii = SI_INFO(sih);
if (PMUCTL_ENAB(sih)) {
INTR_OFF(sii, intr_val);
- fpdelay = si_pmu_fast_pwrup_delay(sih, sii->osh);
+ fpdelay = si_pmu_fast_pwrup_delay(sih);
INTR_RESTORE(sii, intr_val);
return fpdelay;
}
slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih));
break;
case PCI_BUS:
- ASSERT((SI_INFO(sih))->osh != NULL);
+ ASSERT((SI_INFO(sih))->pbus != NULL);
slen = snprintf(path, (size_t) size, "pci/%u/%u/",
((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
PCI_SLOT(
switch (sih->bustype) {
case PCI_BUS:
- ASSERT(sii->osh != NULL);
+ ASSERT(sii->pbus != NULL);
pci_read_config_dword(sii->pbus, PCI_CFG_VID, &w);
if ((w & 0xFFFF) != VENDOR_BROADCOM)
return true;
bool si_is_otp_powered(si_t *sih)
{
if (PMUCTL_ENAB(sih))
- return si_pmu_is_otp_powered(sih, si_osh(sih));
+ return si_pmu_is_otp_powered(sih);
return true;
}
void si_otp_power(si_t *sih, bool on)
{
if (PMUCTL_ENAB(sih))
- si_pmu_otp_power(sih, si_osh(sih), on);
+ si_pmu_otp_power(sih, on);
udelay(1000);
}
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / commitdiff