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MIPS: traps: Dump the PageGrain and Wired registers on MC
author
Markos Chandras
<markos.chandras@imgtec.com>
Wed, 12 Nov 2014 09:23:11 +0000
(09:23 +0000)
committer
Ralf Baechle
<ralf@linux-mips.org>
Mon, 24 Nov 2014 06:45:31 +0000
(07:45 +0100)
They can be useful to determine how the MMU is configured on a MC
exception.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8401/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/traps.c
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diff --git
a/arch/mips/kernel/traps.c
b/arch/mips/kernel/traps.c
index 807def5ab5ed586bcbc09c4a20e96ef1438d93b2..ad3d2031c327737f64c53a43ab6264a20ca5a354 100644
(file)
--- a/
arch/mips/kernel/traps.c
+++ b/
arch/mips/kernel/traps.c
@@
-1432,6
+1432,8
@@
asmlinkage void do_mcheck(struct pt_regs *regs)
pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
+ pr_err("Wired : %0x\n", read_c0_wired());
+ pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
if (cpu_has_htw) {
pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
pr_err("PWSize : %0*lx\n", field, read_c0_pwsize());